//CONFIG2_ID
enum PHYTYPE {
HDMI_TX_PHY = 0x00,
- MHL_WITH_HEAC_PHY = 0xb2,
- MHL_PHY = 0xc2,
+ HDMI_MHL_WITH_HEAC_PHY = 0xb2,
+ HDMI_MHL_PHY = 0xc2,
HDMI_3D_TX_WITH_HEAC_PHY = 0xe2,
HDMI_3D_TX_PHY = 0xf2
};
#define m_AVI_MUTE (1 << 1)
#define m_GCP_MUTE (1 << 0)
+//IH_MUTE_FC_STAT2
+#define m_LPRIO_OVERFLOW_MUTE (1 << 1)
+#define m_HPRIO_OVERFLOW_MUTE (1 << 0)
+
+//IH_MUTE_AS_STAT0
+#define m_FIFO_UNDERRUN_MUTE (1 << 4)
+#define m_FIFO_OVERRUN_MUTE (1 << 3)
+#define m_AUD_FIFO_UDF_THR_MUTE (1 << 2)
+#define m_AUD_FIFO_UDF_MUTE (1 << 1)
+#define m_AUD_FIFO_OVF_MUTE (1 << 0)
+
+//IH_MUTE_PHY_STAT0
+#define m_RX_SENSE3_MUTE (1 << 5)
+#define m_RX_SENSE2_MUTE (1 << 4)
+#define m_RX_SENSE1_MUTE (1 << 3)
+#define m_RX_SENSE0_MUTE (1 << 2)
+#define m_TX_PHY_LOCK_MUTE (1 << 1)
+#define m_HPD_MUTE (1 << 0)
+
+//IH_MUTE_I2CM_STAT0
+#define m_SCDC_READREQ_MUTE (1 << 2)
+#define m_I2CM_DONE_MUTE (1 << 1)
+#define m_I2CM_ERR_MUTE (1 << 0)
+
+//IH_MUTE_CEC_STAT0
+#define m_WAKEUP_MUTE (1 << 6)
+#define m_ERR_FOLLOW_MUTE (1 << 5)
+#define m_ERR_INITIATOR_MUTE (1 << 4)
+#define m_ARB_LOST_MUTE (1 << 3)
+#define m_NACK_MUTE (1 << 2)
+#define m_EOM_MUTE (1 << 1)
+#define m_DONE_MUTE (1 << 0)
+
+//IH_MUTE_VP_STAT0
+#define m_FIFOFULL_REP_MUTE (1 << 7)
+#define m_FIFOEMPTY_REP_MUTE (1 << 6)
+#define m_FIFOFULL_PACK_MUTE (1 << 5)
+#define m_FIFOEMPTY_PACK_MUTE (1 << 4)
+#define m_FIFOFULL_REMAP_MUTE (1 << 3)
+#define m_FIFOEMPTY_REMAP_MUTE (1 << 2)
+#define m_FIFOFULL_BYP_MUTE (1 << 1)
+#define m_FIFOEMPTY_BYP_MUTE (1 << 0)
+
+//IH_MUTE_I2CMPHY_STAT0
+#define m_I2CMPHY_DONE_MUTE (1 << 1)
+#define m_I2CMPHY_ERR_MUTE (1 << 0)
/*Video Sampler Registers*/
#define VIDEO_SAMPLER_BASE 0x0200
-enum {
+enum VIDEO_SAMPLER_REG {
TX_INVID0 = VIDEO_SAMPLER_BASE,
TX_INSTUFFING,
TX_GYDATA0,
TX_BCBDATA1
};
+//TX_INVID0
+#define m_INTERNAL_DE_GEN (1 << 7)
+#define v_INTERNAL_DE_GEN(n) (((n)&0x01) << 7)
+enum VIDEO_MODE{
+ VIDEO_RGB444_8BIT = 0x01,
+ VIDEO_RGB444_10BIT = 0x03,
+ VIDEO_RGB444_12BIT = 0x05,
+ VIDEO_RGB444_16BIT = 0x07,
+ VIDEO_YCBCR444_8BIT = 0x09, //or YCbCr420
+ VIDEO_YCBCR444_10BIT = 0x0b, //or YCbCr420
+ VIDEO_YCBCR444_12BIT = 0x0d, //or YCbCr420
+ VIDEO_YCBCR444_16BIT = 0x0f, //or YCbCr420
+ VIDEO_YCBCR422_12BIT = 0x12,
+ VIDEO_YCBCR422_10BIT = 0x14,
+ VIDEO_YCBCR422_8BIT = 0x16
+};
+#define m_VIDEO_MAPPING (0x1f << 0)
+#define v_VIDEO_MAPPING(n) ((n)&0x1f)
+
+//TX_INSTUFFING
+#define m_BCBDATA_STUFF (1 << 2)
+#define v_BCBDATA_STUFF(n) (((n)&0x01) << 2)
+#define m_RCRDATA_STUFF (1 << 1)
+#define v_RCRDATA_STUFF(n) (((n)&0x01) << 1)
+#define m_GYDATA_STUFF (1 << 0)
+#define v_GYDATA_STUFF(n) (((n)&0x01) << 0)
+
+
/*Video Packetizer Registers*/
#define VIDEO_PACKETIZER_BASE 0x0800
-enum {
+enum VIDEO_PACKETIZER_REG {
VP_STATUS = VIDEO_PACKETIZER_BASE,
VP_PR_CD,
VP_STUFF,
VP_MASK = 0x0807
};
+//VP_STATUS
+#define m_PACKING_PHASE (0x0f << 0)
+
+//VP_PR_CD
+enum COLOR_DEPTH {
+ COLOR_DEPTH_24BIT_DEFAULT = 0,
+ COLOR_DEPTH_24BIT = 0x04,
+ COLOR_DEPTH_30BIT,
+ COLOR_DEPTH_36BIT,
+ COLOR_DEPTH_48BIT
+};
+#define m_COLOR_DEPTH (0x0f << 4)
+#define v_COLOR_DEPTH(n) (((n)&0x0f) << 4)
+enum PIXEL_REPET {
+ NO_PIXEL_REPET = 0,
+ PIXEL_SENT_2TIMES,
+ PIXEL_SENT_3TIMES,
+ PIXEL_SENT_4TIMES,
+ PIXEL_SENT_5TIMES,
+ PIXEL_SENT_6TIMES,
+ PIXEL_SENT_7TIMES,
+ PIXEL_SENT_8TIMES,
+ PIXEL_SENT_9TIMES,
+ PIXEL_SENT_10TIMES
+};
+#define m_DESIRED_PR_FACTOR (0x07 << 0)
+#define v_DESIRED_PR_FACTOR(n) (((n)&0x07) << 0)
+
+//VP_STUFF
+#define m_IDEFAULT_PHASE (1 << 5)
+#define v_IDEFAULT_PHASE(n) (((n)&0x01) << 5)
+#define m_IFIX_PP_TO_LAST (1 << 4)
+#define m_ICX_GOTO_P0_ST (1 << 3)
+enum {
+ DIRECT_MODE = 0,
+ STUFFING_MODE
+};
+#define m_YCC422_STUFFING (1 << 2)
+#define v_YCC422_STUFFING(n) (((n)&0x01) << 1)
+#define m_PR_STUFFING (1 << 0)
+#define v_PR_STUFFING(n) (((n)&0x01) << 0)
+
+//VP_REMAP
+enum YCC422_SIZE{
+ YCC422_16BIT = 0,
+ YCC422_20BIT,
+ YCC422_24BIT
+};
+#define m_YCC422_SIZE (0x03 << 0)
+#define v_YCC422_SIZE(n) (((n)&0x03) << 0)
+
+//VP_CONF
+#define m_BYPASS_EN (1 << 6)
+#define v_BYPASS_EN(n) (((n)&0x01) << 6)
+#define m_PIXEL_PACK_EN (1 << 5)
+#define v_PIXEL_PACK_EN(n) (((n)&0x01) << 5)
+#define m_PIXEL_REPET_EN (1 << 4)
+#define v_PIXEL_REPET_EN(n) (((n)&0x01) << 4)
+#define m_YCC422_EN (1 << 3)
+#define v_YCC422_EN(n) (((n)&0x01) << 3)
+#define m_BYPASS_SEL (1 << 2)
+#define v_BYPASS_SEL(n) (((n)&0x01) << 2)
+enum {
+ OUT_FROM_PIXEL_PACKING = 0,
+ OUT_FROM_YCC422_REMAP,
+ OUT_FROM_8BIT_BYPASS
+};
+#define m_OUTPUT_SEL (0x03 << 0)
+#define v_OUTPUT_SEL(n) ((n&0x03) << 0)
+
+//VP_MASK
+#define m_OINTFULL_REPET (1 << 7)
+#define m_OINTEMPTY_REPET (1 << 6)
+#define m_OINTFULL_PACK (1 << 5)
+#define m_OINTEMPTY_PACK (1 << 4)
+#define m_OINTFULL_REMAP (1 << 3)
+#define m_OINTEMPTY_REMAP (1 << 2)
+#define m_OINTFULL_BYPASS (1 << 1)
+#define m_OINTEMPTY_BYPASS (1 << 0)
+
+
/*Frame Composer Registers*/
#define FRAME_COMPOSER_BASE 0x1000
-enum {
+enum FRAME_COMPOSER_REG {
FC_INVIDCONF = FRAME_COMPOSER_BASE,
FC_INHACTIV0,
FC_INHACTIV1,
/*HDMI Source PHY Registers*/
#define HDMI_SOURCE_PHY_BASE 0x3000
-enum {
+enum HDMI_SOURCE_PHY_REG {
PHY_CONF0 = HDMI_SOURCE_PHY_BASE,
PHY_TST0,
PHY_TST1,
PHY_PLLCFGFREQ2
};
+//PHY_CONF0
+#define m_POWER_DOWN_EN (1 << 7) //enable depend on PHY_GEN2=0 and PHY_EXTERNAL=0
+#define v_POWER_DOWN_EN(n) (((n)&0x01) << 7)
+#define m_TMDS_EN (1 << 6) //enable depend on PHY_GEN2=0 and PHY_EXTERNAL=0
+#define m_TMDS_EN(n) (((n)&0x01) << 6)
+#define m_SVSRET_SIG (1 << 5) //depend on PHY_MHL_COMB0=1
+#define v_SVSRET_SIG(n) (((n)&0x01) << 5)
+#define m_PDDQ_SIG (1 << 4) //depend on PHY_GEN2=1 or PHY_EXTERNAL=1
+#define v_PDDQ_SIG(n) (((n)&0x01) << 4)
+#define m_TXPWRON_SIG (1 << 3) //depend on PHY_GEN2=1 or PHY_EXTERNAL=1
+#define v_TXPWRON_SIG(n) (((n)&0x01) << 3)
+#define m_ENHPD_RXSENSE_SIG (1 << 2) //depend on PHY_GEN2=1 or PHY_EXTERNAL=1
+#define v_ENHPD_RXSENSE_SIG (((n)&0x01) << 2)
+#define m_SEL_DATAEN_POL (1 << 1)
+#define v_SEL_DATAEN_POL(n) (((n)&0x01) << 1)
+#define m_SEL_INTERFACE (1 << 0)
+#define v_SEL_INTERFACE(n) (((n)&0x01) << 0)
+
+//PHY_TST0
+#define m_TEST_CLR_SIG (1 << 5)
+#define m_TEST_EN_SIG (1 << 4)
+#define m_TEST_CLK_SIG (1 << 0)
+
+//PHY_STAT0/PHY_INI0/PHY_MASK/PHY_POL0
+#define m_PHY_RX_SENSE3 (1 << 7)
+#define v_PHY_TX_SENSE3(n) (((n)&0x01) << 7)
+#define m_PHY_RX_SENSE2 (1 << 6)
+#define v_PHY_TX_SENSE2(n) (((n)&0x01) << 6)
+#define m_PHY_RX_SENSE1 (1 << 5)
+#define v_PHY_TX_SENSE1(n) (((n)&0x01) << 5)
+#define m_PHY_RX_SENSE0 (1 << 4)
+#define v_PHY_TX_SENSE0(n) (((n)&0x01) << 4)
+#define m_PHY_HPD (1 << 1)
+#define v_PHY_HPD (((n)&0x01) << 1)
+#define m_PHY_LOCK (1 << 0)
+#define v_PHY_LOCK(n) (((n)&0x01) << 0)
+
+
/*I2C Master PHY Registers*/
#define I2C_MASTER_PHY_BASE 0x3020
-enum {
+enum I2C_MASTER_PHY_REG {
PHY_I2CM_SLAVE = I2C_MASTER_PHY_BASE,
PHY_I2CM_ADDRESS,
PHY_I2CM_DATAO_1,
I2CM_PHY_SDA_HOLD
};
+//PHY_I2CM_OPERATION
+#define v_I2CM_WRITE (1 << 4)
+#define v_I2CM_READ (1 << 0)
+
+//PHY_I2CM_INT
+#define m_I2CM_DONE_INT_POL (1 << 3)
+#define v_I2CM_DONE_INT_POL(n) (((n)&0x01) << 3)
+#define m_I2CM_DONE_MASK (1 << 2)
+#define v_I2CM_DONE_MASK(n) (((n)&0x01) << 2)
+#define m_I2CM_DONE_INT (1 << 1)
+#define m_I2CM_DONE_STATUS (1 << 0)
+
+//PHY_I2CM_CTLINT
+#define m_I2CM_NACK_POL (1 << 7)
+#define v_I2CM_NACK_POL(n) (((n)&0x01) << 7)
+#define m_I2CM_NACK_MASK (1 << 6)
+#define v_I2CM_NACK_MASK(n) (((n)&0x01) << 6)
+#define m_I2CM_NACK_INT (1 << 5)
+#define m_I2CM_NACK_STATUS (1 << 4)
+#define m_I2CM_ARB_POL (1 << 3)
+#define v_I2CM_ARB_POL(n) (((n)&0x01) << 3)
+#define m_I2CM_ARB_MASK (1 << 2)
+#define v_I2CM_ARB_MASK(n) (((n)&0x01) << 2)
+#define m_I2CM_ARB_INT (1 << 1)
+#define m_I2CM_ARB_STATUS (1 << 0)
+
+//PHY_I2CM_DIV
+enum {
+ STANDARD_MODE = 0,
+ FAST_MODE
+};
+#define m_I2CM_FAST_STD_MODE (1 << 3)
+#define v_I2CM_FAST_STD_MODE (((n)&0x01) << 3)
+
+//PHY_I2CM_SOFTRSTZ
+#define m_I2CM_SOFTRST (1 << 0)
+#define v_I2CM_SOFTRST (((n)&0x01) << 0)
+
+
/*Audio Sampler Registers*/
#define AUDIO_SAMPLER_BASE 0x3100
-enum {
+enum AUDIO_SAMPLER_REG {
AUD_CONF0 = AUDIO_SAMPLER_BASE,
AUD_CONF1,
AUD_INT,
AUD_SPDIFINT1
};
+//AUD_CONF0
+#define m_SW_AUD_FIFO_RST (1 << 7)
+#define v_SW_AUD_FIFO_RST(n) (((n)&0x01) << 7)
+enum {
+ AUDIO_SPDIF_GPA = 0,
+ AUDIO_I2S
+};
+#define m_I2S_SEL (1 << 5)
+#define v_I2S_SEL(n) (((n)&0x01) << 5)
+#define m_I2S_IN_EN (0x0f << 0)
+#define v_I2S_IN_EN(v) (((n)&0x0f) << 0)
+
+//AUD_CONF1
+enum I2S_MODE {
+ I2S_STANDARD_MODE = 0,
+ I2S_RIGHT_JUSTIFIED_MODE,
+ I2S_LEFT_JUSTIFIED_MODE,
+ I2S_BURST_1_MODE,
+ I2S_BURST_2_MODE
+};
+#define m_I2S_MODE (0x07 << 5)
+#define v_I2S_MODE(n) (((n)&0x07) << 5)
+enum I2S_WIDTH {
+ I2S_16BIT_SAMPLE = 16,
+ I2S_17BIT_SAMPLE,
+ I2S_18BIT_SAMPLE,
+ I2S_19BIT_SAMPLE,
+ I2S_20BIT_SAMPLE,
+ I2S_21BIT_SAMPLE,
+ I2S_22BIT_SAMPLE,
+ I2S_23BIT_SAMPLE,
+ I2S_24BIT_SAMPLE,
+};
+#define m_I2S_WIDTH (0x1f << 0)
+#define v_I2S_WIDTH(n) (((n)&0x1f) << 0)
+
+//AUD_INT/AUD_SPDIFINT
+#define m_FIFO_EMPTY_MASK (1 << 3)
+#define v_FIFO_EMPTY_MASK(n) (((n)&0x01) << 3)
+#define m_FIFO_FULL_MASK (1 << 2)
+#define v_FIFO_FULL_MASK(n) (((n)&0x01) << 2)
+
+//AUD_CONF2
+#define m_NLPCM_EN (1 << 1)
+#define v_NLPCM_EN(n) (((n)&0x01) << 1)
+#define m_HBR_EN (1 << 0)
+#define v_HBR_EN(n) (((n)&0x01) << 0)
+
+//AUD_INT1/AUD_SPDIFINT1
+#define m_FIFO_OVERRUN_MASK (1 << 4)
+#define v_FIFO_OVERRUN_MASK(n) (((n)&0x01) << 4)
+
+//AUD_N3
+#define m_NCTS_ATOMIC_WR (1 << 7)
+#define v_NCTS_ATOMIC_WR(n) (((n)&0x01) << 7)
+#define m_AUD_N3 (0x0f << 0)
+#define v_AUD_N3(n) (((n)&0x0f) << 0)
+
+//AUD_CTS3
+enum {
+ N_SHIFT_1 = 0,
+ N_SHIFT_16,
+ N_SHIFT_32,
+ N_SHIFT_64,
+ N_SHIFT_128,
+ N_SHIFT_256,
+ N_SHIFT_OTHERS_128
+};
+#define m_N_SHIFT (0x07 << 5)
+#define v_N_SHIFT(n) (((n)&0x07) << 5)
+#define m_CTS_MANUAL (1 << 4)
+#define v_CTS_MANUAL(n) (((n)&0x01) << 4)
+#define m_AUD_CTS3 (0x0f << 0)
+#define v_AUD_CTS3(n) (((n)&0x0f) << 0)
+
+//AUD_INPUTCLKFS
+enum {
+ FS_128 = 0,
+ FS_256,
+ FS_512,
+ FS_64 = 4,
+ FS_OTHERS_128
+};
+#define m_LFS_FACTOR (0x07 << 0)
+#define v_LFS_FACTOR(n) (((n)&0x07) << 0)
+
+//AUD_SPDIF0
+#define m_SW_SAUD_FIFO_RST (1 << 7)
+#define v_SW_SAUD_FIFO_RST (((n)&0x01) << 7)
+
+//AUD_SPDIF1
+#define m_SET_NLPCM (1 << 7)
+#define v_SET_NLPCM (((n)&0x01) << 7)
+#define m_SPDIF_HBR_MODE (1 << 6)
+#define v_SPDIF_HBR_MODE(n) (((n)&0x01) << 6)
+#define m_SPDIF_WIDTH (0x1f << 0)
+#define v_SPDIF_WIDTH(n) (((n)&0x1f) << 0)
+
+
/*Generic Parallel Audio Interface Registers*/
#define GP_AUDIO_INTERFACE_BASE 0x3500
-enum {
+enum GP_AUDIO_INTERFACE_REG {
GP_CONF0 = GP_AUDIO_INTERFACE_BASE,
GP_CONF1,
GP_CONF2,
/*Audio DMA Registers*/
#define AUDIO_DMA_BASE 0x3600
-enum {
+enum AUDIO_DMA_REG {
AHB_DMA_CONF0 = AUDIO_DMA_BASE,
AHB_DMA_START,
AHB_DMA_STOP,
/*Main Controller Registers*/
#define MAIN_CONTROLLER_BASE 0X4000
-enum {
+enum MAIN_CONTROLLER_REG {
MC_CLKDIS = 0x4001,
MC_SWRSTZREQ,
MC_OPCTRL,
MC_SWRSTZREQ_2
};
+//MC_CLKDIS
+#define m_HDCPCLK_DISABLE (1 << 6)
+#define v_HDCPCLK_DISABLE(n) (((n)&0x01) << 6)
+#define m_CECCLK_DISABLE (1 << 5)
+#define v_CECCLK_DISABLE(n) (((n)&0x01) << 5)
+#define m_CSCCLK_DISABLE (1 << 4)
+#define v_CSCCLK_DISABLE(n) (((n)&0x01) << 4)
+#define m_AUDCLK_DISABLE (1 << 3)
+#define v_AUDCLK_DISABLE(n) (((n)&0x01) << 3)
+#define m_PREPCLK_DISABLE (1 << 2)
+#define v_PREPCLK_DISABLE(n) (((n)&0x01) << 2)
+#define m_TMDSCLK_DISABLE (1 << 1)
+#define v_TMDSCLK_DISABLE(n) (((n)&0x01) << 1)
+#define m_PIXELCLK_DISABLE (1 << 0)
+#define v_PIXELCLK_DISABLE(n) (((n)&0x01) << 0)
+
+//MC_SWRSTZREQ
+#define m_IGPA_SWRST (1 << 7)
+#define v_IGPA_SWRST(n) (((n)&0x01) << 7)
+#define m_CEC_SWRST (1 << 6)
+#define v_CEC_SWRST(n) (((n)&0x01) << 6)
+#define m_ISPDIF_SWRST (1 << 4)
+#define v_ISPDIF_SWRST(n) (((n)&0x01) << 4)
+#define m_II2S_SWRST (1 << 3)
+#define v_II2S_SWRST(n) (((n)&0x01) << 3)
+#define m_PREP_SWRST (1 << 2)
+#define v_PREP_SWRST(n) (((n)&0x01) << 2)
+#define m_TMDS_SWRST (1 << 1)
+#define v_TMDS_SWRST(n) (((n)&0x01) << 1)
+#define m_PIXEL_SWRST (1 << 0)
+#define v_PIXEL_SWRST(n) (((n)&0x01) << 0)
+
+//MC_OPCTRL
+#define m_HDCP_BLOCK_BYP (1 << 0)
+#define v_HDCP_BLOCK_BYP(n) (((n)&0x01) << 0)
+
+//MC_FLOWCTRL
+#define m_FEED_THROUGH_OFF (1 << 0)
+#define v_FEED_THROUGH_OFF(n) (((n)&0x01) << 0)
+
+//MC_PHYRSTZ
+#define m_PHY_RSTZ (1 << 0)
+#define v_PHY_RSTZ(n) (((n)&0x01) << 0)
+
+//MC_LOCKONCLOCK
+#define m_IGPACLK_ON (1 << 7)
+#define v_IGPACLK_ON(n) (((n)&0x01) << 7)
+#define m_PCLK_ON (1 << 6)
+#define v_PCLK_ON(n) (((n)&0x01) << 6)
+#define m_TMDSCLK_ON (1 << 5)
+#define v_TMDSCLK_ON(n) (((n)&0x01) << 5)
+#define m_PREPCLK_ON (1 << 4)
+#define v_PREPCLK_ON(n) (((n)&0x01) << 4)
+#define m_I2SCLK_ON (1 << 3)
+#define v_I2SCLK_ON(n) (((n)&0x01) << 3)
+#define m_SPDIFCLK_ON (1 << 2)
+#define v_SPDIFCLK_ON(n) (((n)&0x01) << 2)
+#define m_CECCLK_ON (1 << 0)
+#define v_CECCLK_ON(n) (((n)&0x01) << 0)
+
+//MC_HEACPHY_RST
+#define m_HEAC_PHY_RST (1 << 0)
+#define v_HEAC_PHY_RST(n) (((n)&0x01) << 0)
+
+//MC_LOCKONCLOCK_2
+#define m_AHB_AUD_DMA_CLK (1 << 0)
+#define v_AHB_AUD_DMA_CLK(n) (((n)&0x01) << 0)
+
+//MC_SWRSTZREQ_2
+#define m_AHB_AUD_DMA_RST (1 << 7)
+#define v_AHB_AUD_DMA_RST(n) (((n)&0x01) << 7)
+
+
/*Color Space Converter Registers*/
#define COLOR_SPACE_CONVERTER_BASE 0x4100
-enum {
+enum COLOR_SPACE_CONVERTER_REG {
CSC_CFG = COLOR_SPACE_CONVERTER_BASE,
CSC_SCALE,
CSC_COEF_A1_MSB
CSC_SPARE_2
};
+//CSC_CFG
+#define m_INTMODE (0x03 << 4)
+#define v_INTMODE(n) (((n)&0x03) << 4)
+#define m_DECMODE (0x03 << 0)
+#define v_DECMODE(n) (((n)&0x03) << 0)
+
+//CSC_SCALE
+#define m_CSC_COLOR_DEPTH (0x0f << 4)
+#define v_CSC_COLOR_DEPTH (((n)&0x0f) >> 4)
+#define m_CSC_SCALE (0x03 << 0)
+#define v_CSC_SCALE (((n)&0x03) >> 0)
+
+
+
/*HDCP Encryption Engine Registers*/
#define HDCP_ENCRYPTION_ENGINE_BASE 0x5000
-enum {
+enum HDCP_ENCRYPTION_REG {
A_HDCPCFG0 = HDCP_ENCRYPTION_ENGINE_BASE,
A_HDCPCFG1,
A_HDCPOBS0,
/*HDCP BKSV Registers*/
#define HDCP_BKSV_BASE 0x7800
-enum {
+enum HDCP_BKSV_REG {
HDCPREG_BKSV0 = HDCP_BKSV_BASE,
HDCPREG_BKSV1,
HDCPREG_BKSV2,
/*HDCP AN Registers*/
#define HDCP_AN_BASE 0x7805
-enum {
+enum HDCP_AN_REG {
HDCPREG_ANCONF = HDCP_AN_BASE,
HDCPREG_AN0,
HDCPREG_AN1,
/*Encrypted DPK Embedded Storage Registers*/
#define ENCRYPTED_DPK_EMBEDDED_BASE 0x780e
-enum {
+enum ENCRYPTED_DPK_EMBEDDED_REG {
HDCPREG_RMCTL = ENCRYPTED_DPK_EMBEDDED_BASE,
HDCPREG_RMSTS,
HDCPREG_SEED0,
/*CEC Engine Registers*/
#define CEC_ENGINE_BASE 0x7d00
-enum {
+enum CEC_ENGINE_REG {
CEC_CTRL = CEC_ENGINE_BASE,
CEC_MASK = 0x7d02,
CEC_ADDR_L = 0x7d05,
/*I2C Master Registers*/
#define I2C_MASTER_BASE 0x7e00
-enum {
+enum I2C_MASTER_REG {
I2CM_SLAVE = I2C_MASTER_BASE,
I2CM_ADDRESS,
I2CM_DATAO,
-extern struct hdmi *hdmi;
-static inline int hdmi_readl(u16 offset, u32 *val)
+static inline int hdmi_readl(struct hdmi *hdmi_drv, u16 offset, u32 *val)
{
int ret = 0;
- *val = readl_relaxed(hdmi->regbase + (offset) * 0x04);
+ *val = readl_relaxed(hdmi_drv->regbase + (offset) * 0x04);
return ret;
}
-static inline int hdmi_writel(u16 offset, u32 val)
+static inline int hdmi_writel(struct hdmi *hdmi_drv, u16 offset, u32 val)
{
int ret = 0;
- writel_relaxed(val, hdmi->regbase + (offset) * 0x04);
+ writel_relaxed(val, hdmi_drv->regbase + (offset) * 0x04);
return ret;
}
-static inline int hdmi_msk_reg(u16 offset, u32 msk, u32 val)
+static inline int hdmi_msk_reg(struct hdmi *hdmi_drv, u16 offset, u32 msk, u32 val)
{
int ret = 0;
u32 temp;
- temp = readl_relaxed(hdmi->regbase + (offset) * 0x04) & (0xFF - (msk));
- writel_relaxed(temp | ( (val) & (msk) ), hdmi->regbase + (offset) * 0x04);
+ temp = readl_relaxed(hdmi_drv->regbase + (offset) * 0x04) & (0xFF - (msk));
+ writel_relaxed(temp | ( (val) & (msk) ), hdmi_drv->regbase + (offset) * 0x04);
return ret;
}
-static inline void rk3028_hdmi_reset_pclk(void)
-{
- writel_relaxed(0x00010001,RK2928_CRU_BASE+ 0x128);
- msleep(100);
- writel_relaxed(0x00010000, RK2928_CRU_BASE + 0x128);
-}
#endif
projects / firefly-linux-kernel-4.4.55.git / commitdiff