drm/i915/dp: Flush the PLL register write before sleeping
authorChris Wilson <chris@chris-wilson.co.uk>
Wed, 8 Sep 2010 20:07:28 +0000 (21:07 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Wed, 8 Sep 2010 20:20:27 +0000 (21:20 +0100)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_dp.c

index 27805a9ca877feadb743c57039e1cef084df5520..c7aa29bfdea995e7120a67903a56d5489a5ece95 100644 (file)
@@ -883,6 +883,7 @@ static void ironlake_edp_pll_off(struct drm_encoder *encoder)
        dpa_ctl = I915_READ(DP_A);
        dpa_ctl |= DP_PLL_ENABLE;
        I915_WRITE(DP_A, dpa_ctl);
+       POSTING_READ(DP_A);
        udelay(200);
 }