ARM: tegra: common: Reduce sclk to 120 MHz

Set pll_m_out1, sclk, and hclk to 120 MHz, and pclk to 60 MHz.
Drivers that require a faster bus speed can use a shared bus clock
reference to increase the sclk frequency up to 240 MHz, which will
also increase pll_m_out1, hclk, and pclk.

Change-Id: Ic491da80de1d95e6550cf9351eae185210f55b2a
Signed-off-by: Colin Cross <ccross@android.com>

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 82bca0ccb223cde4e20efb97d6028cdcab507b58..2fdb99b6fdc5d5363d4206efab1d26ab8d8d7c55 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -59,10 +59,10 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
        { "pll_p_out1", "pll_p",        28800000,       true },
        { "pll_p_out2", "pll_p",        48000000,       true },
        { "pll_p_out3", "pll_p",        72000000,       true },
-       { "pll_m_out1", "pll_m",        240000000,      true },
-       { "sclk",       "pll_m_out1",   240000000,      true },
-       { "hclk",       "sclk",         240000000,      true },
-       { "pclk",       "hclk",         120000000,      true },
+       { "pll_m_out1", "pll_m",        120000000,      true },
+       { "sclk",       "pll_m_out1",   120000000,      true },
+       { "hclk",       "sclk",         120000000,      true },
+       { "pclk",       "hclk",         60000000,       true },
        { "pll_x",      NULL,           0,              true },
        { "cpu",        NULL,           0,              true },
        { "emc",        NULL,           0,              true },