MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.

(cherry picked from commit e65c7f33d75e977350ca350573d93c517ec02776)

Previously it was unconditionally used on all Sibyte family SOCs.  The
M3 bug has to be handled in the TLB exception handler which is extremly
performance sensitive, so this modification is expected to deliver around
2-3% performance improvment.  This is important as required changes to the
M3 workaround will make it more costly.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 7950ef4f032c218a2382be9560c2138b2c05d8a9..743385d7b5f22b36bcea1f0aa740ad923af41ca4 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -16,7 +16,11 @@
 #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
     defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
 
-#define BCM1250_M3_WAR 1
+#ifndef __ASSEMBLY__
+extern int sb1250_m3_workaround_needed(void);
+#endif
+
+#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
 #define SIBYTE_1956_WAR        1
 
 #else

diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 0444da1e23c24e2dc675a40034a2e7adc087ba41..92da3155ce074ac16840c715fde220946a13b4fd 100644 (file)
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -87,6 +87,21 @@ static int __init setup_bcm1250(void)
        return ret;
 }
 
+int sb1250_m3_workaround_needed(void)
+{
+       switch (soc_type) {
+       case K_SYS_SOC_TYPE_BCM1250:
+       case K_SYS_SOC_TYPE_BCM1250_ALT:
+       case K_SYS_SOC_TYPE_BCM1250_ALT2:
+       case K_SYS_SOC_TYPE_BCM1125:
+       case K_SYS_SOC_TYPE_BCM1125H:
+               return soc_pass < K_SYS_REVISION_BCM1250_C0;
+
+       default:
+               return 0;
+       }
+}
+
 static int __init setup_bcm112x(void)
 {
        int ret = 0;