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relax assertion
author
Chris Lattner
<sabre@nondot.org>
Sun, 2 Apr 2006 06:19:46 +0000
(06:19 +0000)
committer
Chris Lattner
<sabre@nondot.org>
Sun, 2 Apr 2006 06:19:46 +0000
(06:19 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27358
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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diff --git
a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 9a2c9a19fb6f02d689844a2957f877ce2fa1a9c0..392b489297514bdfbe34f3feedfd809aa6c7f986 100644
(file)
--- a/
lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/
lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@
-935,7
+935,10
@@
void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const {
- assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
+ assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
+ Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_VOID) &&
"Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!");
KnownZero = 0;