Merge branch 'pm-sr' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman...

diff --combined arch/arm/mach-omap2/control.h
index 208a670c826bdcc05132ff3353952d889ac229f2,b32cf4e341d477a3d5cde0b3741ac18b291ff1d2..f0629ae04102d51e638625277555c39d262ba669
--- 1/arch/arm/mach-omap2/control.h
--- 2/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@@ -148,6 -148,15 +148,15 @@@
  #define OMAP343X_CONTROL_TEST_KEY_11  (OMAP2_CONTROL_GENERAL + 0x00f4)
  #define OMAP343X_CONTROL_TEST_KEY_12  (OMAP2_CONTROL_GENERAL + 0x00f8)
  #define OMAP343X_CONTROL_TEST_KEY_13  (OMAP2_CONTROL_GENERAL + 0x00fc)
+ #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
+ #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
+ #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
+ #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
+ #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
+ #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
+ #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
+ #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
+ #define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
  #define OMAP343X_CONTROL_IVA2_BOOTADDR        (OMAP2_CONTROL_GENERAL + 0x0190)
  #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
  #define OMAP343X_CONTROL_DEBOBS(i)    (OMAP2_CONTROL_GENERAL + 0x01B0 \
@@@ -164,6 -173,26 +173,26 @@@
  #define OMAP343X_CONTROL_SRAMLDO5     (OMAP2_CONTROL_GENERAL + 0x02C0)
  #define OMAP343X_CONTROL_CSI          (OMAP2_CONTROL_GENERAL + 0x02C4)
  
+ /* OMAP3630 only CONTROL_GENERAL register offsets */
+ #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
+ #define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
+ #define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
+ #define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
+ #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
+ #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
+ 
+ /* OMAP44xx control efuse offsets */
+ #define OMAP44XX_CONTROL_FUSE_IVA_OPP50               0x22C
+ #define OMAP44XX_CONTROL_FUSE_IVA_OPP100      0x22F
+ #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO    0x232
+ #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO    0x235
+ #define OMAP44XX_CONTROL_FUSE_MPU_OPP50               0x240
+ #define OMAP44XX_CONTROL_FUSE_MPU_OPP100      0x243
+ #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO    0x246
+ #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO    0x249
+ #define OMAP44XX_CONTROL_FUSE_CORE_OPP50      0x254
+ #define OMAP44XX_CONTROL_FUSE_CORE_OPP100     0x257
+ 
  /* AM35XX only CONTROL_GENERAL register offsets */
  #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
  #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
@@@ -315,7 -344,7 +344,7 @@@
  #define               FEAT_SGX_NONE           2
  
  #define OMAP3_IVA_SHIFT                       12
 -#define OMAP3_IVA_MASK                        (1 << OMAP3_SGX_SHIFT)
 +#define OMAP3_IVA_MASK                        (1 << OMAP3_IVA_SHIFT)
  #define               FEAT_IVA                0
  #define               FEAT_IVA_NONE           1