Added the x86 INT instructions; both the special-case INT 3 and the general-case

INT i8.  These instructions are only for interpretation by disassemblers, not
for emission, so they do not as yet have patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78630 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 36db7a18cf34683e8bfb836d83c4ceb0d5288789..903b3ff60a7336cbbcd8e73467f526617827c151 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -518,6 +518,10 @@ let neverHasSideEffects = 1 in {
                 "nopl\t$zero", []>, TB;
 }
 
+// Trap
+def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
+def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
+
 // PIC base
 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
   def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),