Fix construction of ioport intrinsics, fixing X86/io.llx and io-port.llx

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22026 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 52bcc9ab75c8ee038dc9013b4a1c70fede9871fe..2e3febade9ad43985ba2cbf7dbe28549772a7be0 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -711,14 +711,20 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
       case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
 
       case Intrinsic::readport:
-      case Intrinsic::readio:
+      case Intrinsic::readio: {
+        std::vector<MVT::ValueType> VTs;
+        VTs.push_back(TLI.getValueType(I.getType()));
+        VTs.push_back(MVT::Other);
+        std::vector<SDOperand> Ops;
+        Ops.push_back(getRoot());
+        Ops.push_back(getValue(I.getOperand(1)));
         Tmp = DAG.getNode(F->getIntrinsicID() == Intrinsic::readport ?
-                          ISD::READPORT : ISD::READIO,
-                          TLI.getValueType(I.getType()), getRoot(),
-                          getValue(I.getOperand(1)));
+                          ISD::READPORT : ISD::READIO, VTs, Ops);
+                          
         setValue(&I, Tmp);
         DAG.setRoot(Tmp.getValue(1));
         return;
+      }
       case Intrinsic::writeport:
       case Intrinsic::writeio:
         DAG.setRoot(DAG.getNode(F->getIntrinsicID() == Intrinsic::writeport ?