drm/i915 invalidate indirect state pointers at end of ring exec
authorZou Nan hai <nanhai.zou@intel.com>
Fri, 25 Jun 2010 05:40:24 +0000 (13:40 +0800)
committerEric Anholt <eric@anholt.net>
Mon, 9 Aug 2010 18:28:03 +0000 (11:28 -0700)
This is required by the spec, and without this some 3D programs will
hang after resume from RC6 we enable that.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c

index f19ffe87af3c3fbcef67e03a25a6e4a22e5fe133..44af317731b67071c3fa9ec13280975ae7f7d639 100644 (file)
@@ -499,6 +499,13 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
                }
        }
 
+
+       if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
+               BEGIN_LP_RING(2);
+               OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
+               OUT_RING(MI_NOOP);
+               ADVANCE_LP_RING();
+       }
        i915_emit_breadcrumb(dev);
 
        return 0;
index 97a35a42da28b93e67c888cd81bef18d5eec7379..21fd657663aa3472c3cace097c0ee3c9f36ae93d 100644 (file)
 #define   MI_NO_WRITE_FLUSH    (1 << 2)
 #define   MI_SCENE_COUNT       (1 << 3) /* just increment scene count */
 #define   MI_END_SCENE         (1 << 4) /* flush binner and incr scene count */
+#define   MI_INVALIDATE_ISP    (1 << 5) /* invalidate indirect state pointers */
 #define MI_BATCH_BUFFER_END    MI_INSTR(0x0a, 0)
 #define MI_REPORT_HEAD         MI_INSTR(0x07, 0)
 #define MI_OVERLAY_FLIP                MI_INSTR(0x11,0)
index 7823b964817677fc45098a0e0e9b4b759ad91491..51e9c9e718c4c16453659ef873f7d30b88f18f9e 100644 (file)
@@ -535,7 +535,16 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
                intel_ring_advance(dev, ring);
        }
 
+       if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
+               intel_ring_begin(dev, ring, 2);
+               intel_ring_emit(dev, ring, MI_FLUSH |
+                               MI_NO_WRITE_FLUSH |
+                               MI_INVALIDATE_ISP );
+               intel_ring_emit(dev, ring, MI_NOOP);
+               intel_ring_advance(dev, ring);
+       }
        /* XXX breadcrumb */
+
        return 0;
 }