rk3036:clk:modify init clocks

diff --git a/arch/arm/boot/dts/rk3036-clocks.dtsi b/arch/arm/boot/dts/rk3036-clocks.dtsi
index 9b48f81ee543cef3f0d9c09d183fb11360a06ad1..95e06abf31777aae6b63d94e20e7cd865f233733 100755 (executable)
--- a/arch/arm/boot/dts/rk3036-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3036-clocks.dtsi
@@ -85,7 +85,7 @@
 
                fixed_factor_cons {
                        compatible = "rockchip,rk-fixed-factor-cons";
-
+/*
                        otgphy0_12m: otgphy0_12m {
                                compatible = "rockchip,rk-fixed-factor-clock";
                                clocks = <&clk_gates1 5>;
@@ -94,7 +94,7 @@
                                clock-mult = <20>;
                                #clock-cells = <0>;
                        };
-
+*/
                        hclk_vcodec: hclk_vcodec {
                                compatible = "rockchip,rk-fixed-factor-clock";
                                clocks = <&aclk_vcodec_pre>;
@@ -822,6 +822,7 @@
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
                                                        <CLKOPS_RATE_MUX_DIV>;
+                                               rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
                                        };
 
                                        /* reg[31:7]: reserved */
@@ -939,7 +940,7 @@
                                        clk_ddr: ddr_clk_pll_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <8 1>;
-                                               clocks = <&clk_gates0 2>, <&clk_gates0 8>;
+                                               clocks = <&clk_dpll>, <&dummy>;
                                                clock-output-names = "clk_ddr";
                                                #clock-cells = <0>;
                                        };
@@ -1078,6 +1079,7 @@
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
                                                        <CLKOPS_RATE_MUX_DIV>;
+                                               rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
                                        };
 
                                        /* reg[13]: reserved */
@@ -1115,7 +1117,7 @@
                                        clk_gpu_pre: clk_gpu_pre_mux {
                                                compatible = "rockchip,rk3188-mux-con";
                                                rockchip,bits = <8 2>;
-                                               clocks = <&dummy>, <&clk_dpll>, <&clk_gpll>;
+                                               clocks = <&dummy>, <&dummy>, <&clk_gpll>;
                                                clock-output-names = "clk_gpu_pre";
                                                #clock-cells = <0>;
                                                #clock-init-cells = <1>;

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index e267b651b6bbea53557770a64fc09ff958f3e03e..4180765ff8899d4f3d8dfc1fc81b7551847bdd6c 100755 (executable)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -196,7 +196,7 @@
                        <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,  
                        <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
                        <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
-                       <&clk_mac_pll &clk_apll>;
+                       <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
                rockchip,clocks-init-rate =
                        <&clk_core 816000000>, <&clk_gpll 594000000>,
                        <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,