#define VPU_REG_NUM_PP (41)
// client type: decoder plus post-process£º101 registers, size 404B
#define VPU_REG_NUM_DEC_PP (VPU_REG_NUM_DEC+VPU_REG_NUM_PP)
-#if defined(CONFIG_ARCH_RK29)
+#if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK2928)
// client type: encoder only: 96 registers, size 384B for rk29
#define VPU_REG_NUM_ENC (96)
#elif defined(CONFIG_ARCH_RK30)
#define REG_NUM_DEC (60)
#define REG_NUM_PP (41)
-#if defined(CONFIG_ARCH_RK29)
+#if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK2928)
#define REG_NUM_ENC (96)
#elif defined(CONFIG_ARCH_RK30)
#define REG_NUM_ENC (164)
#define SIZE_REG(reg) ((reg)*4)
#define DEC_IO_SIZE ((100 + 1) * 4) /* bytes */
-#if defined(CONFIG_ARCH_RK29)
+#if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK2928)
#define ENC_IO_SIZE (96 * 4) /* bytes */
#elif defined(CONFIG_ARCH_RK30)
#define ENC_IO_SIZE (164 * 4) /* bytes */
#endif
#define REG_NUM_DEC_PP (REG_NUM_DEC+REG_NUM_PP)
static const u16 dec_hw_ids[] = { 0x8190, 0x8170, 0x9170, 0x9190, 0x6731 };
-#if defined(CONFIG_ARCH_RK29)
+#if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK2928)
static const u16 enc_hw_ids[] = { 0x6280, 0x7280, 0x8270 };
#define DEC_PHY_OFFSET 0x200
#elif defined(CONFIG_ARCH_RK30)
}
printk("vpu: power off...");
-#ifdef CONFIG_ARCH_RK29
+#if defined(CONFIG_ARCH_RK29)
pmu_set_power_domain(PD_VCODEC, false);
#else
clk_disable(pd_video);
clk_enable(hclk_vepu);
clk_enable(hclk_cpu_vcodec);
udelay(10);
-#ifdef CONFIG_ARCH_RK29
+#if defined(CONFIG_ARCH_RK29)
pmu_set_power_domain(PD_VCODEC, true);
#else
clk_enable(pd_video);