cpu hclk and pclk is 1:1

diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c
index c95809aabbe158ebf99c43b222a510d728c1a90a..4f84d7f6ecab4a389927d5c71d6a43cf0a3eaee7 100644 (file)
--- a/arch/arm/mach-rk30/clock_data.c
+++ b/arch/arm/mach-rk30/clock_data.c
@@ -44,6 +44,7 @@
 #define CLK_FLG_MAX_I2S_49152KHZ       (1<<4)
 //uart 1m\3m
 #define CLK_FLG_UART_1_3M                      (1<<5)
+#define CLK_CPU_HPCLK_11                               (1<<6)
 
 
 
@@ -854,6 +855,19 @@ struct arm_clks_div_set * arm_clks_get_div(u32 rate)
 
 #endif
 
+u32 force_cpu_hpclk_11(u32 clksel1)
+{
+       u8 p_bits=(clksel1&ACLK_PCLK_MSK)>>ACLK_PCLK_OFF;
+       if(p_bits<3)
+       {
+               return ((clksel1&(~(ACLK_HCLK_MSK|AHB2APB_MSK)))|AHB2APB_11|(p_bits<<ACLK_HCLK_OFF));
+       }
+       else
+       {
+               return clksel1;
+       }
+
+}
 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 {
        unsigned long flags;
@@ -863,6 +877,7 @@ static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
        u32 old_aclk_div=0,new_aclk_div,gpll_arm_aclk_div;
        struct arm_clks_div_set *temp_clk_div;
        unsigned long arm_gpll_rate, arm_gpll_lpj;
+       u32 ps_clksel1;
 
        ps = arm_pll_clk_get_best_pll_set(rate,(struct apll_clk_set *)clk->pll->table);
 
@@ -890,6 +905,10 @@ static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
        temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
        if(!temp_clk_div)
                temp_clk_div=&arm_clk_div_tlb[4];
+       if(rk30_clock_flags&CLK_CPU_HPCLK_11)
+       {               
+               temp_clk_div->clksel1=force_cpu_hpclk_11(temp_clk_div->clksel1);        
+       }
        
        gpll_arm_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
        
@@ -958,6 +977,10 @@ static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
        
        pll_wait_lock(pll_id);
 
+       if(rk30_clock_flags&CLK_CPU_HPCLK_11)
+       {       
+               ps_clksel1=force_cpu_hpclk_11(ps->clksel1);
+       }
        //return form slow
        //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
        //a/h/p clk sel
@@ -966,13 +989,13 @@ static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
                if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
                {       
                        cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
-                       cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
+                       cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
                        cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
                        cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
                }
                else 
                {
-                       cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
+                       cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
                        cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
                }
        }
@@ -987,13 +1010,13 @@ static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
                if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
                {       
                        cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
-                       cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
+                       cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
                        cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
                        cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
                }
                else 
                {
-                       cru_writel((ps->clksel1), CRU_CLKSELS_CON(1));
+                       cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
                        cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
                }
        }

diff --git a/arch/arm/mach-rk30/include/mach/board.h b/arch/arm/mach-rk30/include/mach/board.h
index f23e465192654d45ab6ea55bd837c4bedbf9da8a..3d4fca2e795f59cf704b31a15cafaf1b4410b66e 100755 (executable)
--- a/arch/arm/mach-rk30/include/mach/board.h
+++ b/arch/arm/mach-rk30/include/mach/board.h
@@ -128,7 +128,7 @@ enum _codec_pll {
 #define CLK_FLG_MAX_I2S_49152KHZ       (1<<4)
 //uart 1m\3m
 #define CLK_FLG_UART_1_3M                      (1<<5)
-
+#define CLK_CPU_HPCLK_11                               (1<<6)
 
 
 #ifdef CONFIG_RK29_VMAC

diff --git a/arch/arm/mach-rk30/include/mach/cru.h b/arch/arm/mach-rk30/include/mach/cru.h
index be18d23fdb8cbb2a212f13bf577728bb4ed81c7c..22bde5c8fd975f0ef5c29195c2aea84f8f57a02e 100755 (executable)
--- a/arch/arm/mach-rk30/include/mach/cru.h
+++ b/arch/arm/mach-rk30/include/mach/cru.h
@@ -150,12 +150,14 @@ enum rk_plls_id {
 //hclk div
 #define ACLK_HCLK_W_MSK                (3 << 24)
 #define ACLK_HCLK_MSK          (3 << 8)
+#define ACLK_HCLK_OFF          (8)
 #define ACLK_HCLK_11           (0 << 8)
 #define ACLK_HCLK_21           (1 << 8)
 #define ACLK_HCLK_41           (2 << 8)
 // pclk div
 #define ACLK_PCLK_W_MSK                (3 << 28)
 #define ACLK_PCLK_MSK          (3 << 12)
+#define ACLK_PCLK_OFF          (12)
 #define ACLK_PCLK_11           (0 << 12)
 #define ACLK_PCLK_21           (1 << 12)
 #define ACLK_PCLK_41           (2 << 12)