Data32bitsDirective = "\t.word\t";
Data64bitsDirective = 0;
ZeroDirective = "\t.skip\t";
- CommentString = "!";
- ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
+ CommentString = "#";
+ ConstantPoolSection = "\t.text\n";
AlignmentIsInBytes = false;
}
}
void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
- printOperand(MI, OpNo + 1);
- O << ", ";
- printOperand(MI, OpNo);
+ const MachineOperand &MO1 = MI->getOperand(OpNo);
+ const MachineOperand &MO2 = MI->getOperand(OpNo + 1);
+ assert(MO1.isImmediate());
+
+ if (MO2.isConstantPoolIndex()) {
+ printOperand(MI, OpNo + 1);
+ } else if (MO2.isRegister()) {
+ O << '[';
+ printOperand(MI, OpNo + 1);
+ O << ", ";
+ printOperand(MI, OpNo);
+ O << ']';
+ } else {
+ assert(0 && "Invalid Operand Type");
+ }
}
void printOperand(const MachineInstr *MI, int opNum);
def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
}
-def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+let Defs = [R0, R1, R2, R3] in {
+ def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+}
def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
- "ldr $dst, [$addr]",
+ "ldr $dst, $addr",
[(set IntRegs:$dst, (load iaddr:$addr))]>;
def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),