/// instruction that is an inline asm.
void printInlineAsm(const MachineInstr *MI) const;
+ /// printLabel - This method prints a local label used by debug and
+ /// exception handling tables.
+ void printLabel(const MachineInstr *MI) const;
+
/// printBasicBlockLabel - This method prints the label for the specified
/// MachineBasicBlock
virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,
// Operand #2n+3: A TargetConstant, indicating if the reg is a use/def
// Operand #last: Optional, an incoming flag.
INLINEASM,
+
+ // LABEL - Represents a label in mid basic block used to track
+ // locations needed for debug and exception handling tables. This node
+ // returns a chain.
+ // Operand #0 : input chain.
+ // Operand #1 : module unique number use to identify the label.
+ LABEL,
// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
// value, the same type as the pointer type for the system, and an output
// produces a token chain as output.
DEBUG_LOC,
- // DEBUG_LABEL - This node is used to mark a location in the code where a
- // label should be generated for use by the debug information. It takes a
- // token chain as input and then a unique id (provided by MachineDebugInfo.)
- // It produces a token chain as output.
- DEBUG_LABEL,
-
// BUILTIN_OP_END - This must be the last enum value in this list.
BUILTIN_OP_END
};
// Invariant opcodes: All instruction sets have these as their low opcodes.
enum {
PHI = 0,
- INLINEASM = 1
+ INLINEASM = 1,
+ LABEL = 2
};
unsigned getNumOpcodes() const { return NumOpcodes; }
return get(Opcode).getOperandConstraint(OpNum, Constraint);
}
- /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
- /// instruction if it has one. This is used by codegen passes that update
- /// DWARF line number info as they modify the code.
- virtual unsigned getDWARF_LABELOpcode() const {
- return 0;
- }
-
/// Return true if the instruction is a register to register move
/// and leave the source and dest operands in the passed parameters.
virtual bool isMoveInstr(const MachineInstr& MI,
O << "\n\t" << TAI->getInlineAsmEnd() << "\n";
}
+/// printLabel - This method prints a local label used by debug and
+/// exception handling tables.
+void AsmPrinter::printLabel(const MachineInstr *MI) const {
+ if (AsmVerbose) O << "\n";
+ O << TAI->getPrivateGlobalPrefix()
+ << "debug_loc"
+ << MI->getOperand(0).getImmedValue()
+ << ":\n";
+}
+
/// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
/// instruction, using the specified assembler variant. Targets should
/// overried this to format as appropriate.
while (!MBB->succ_empty())
MBB->removeSuccessor(MBB->succ_end()-1);
- // If there is DWARF info to active, check to see if there are any DWARF_LABEL
+ // If there is DWARF info to active, check to see if there are any LABEL
// records in the basic block. If so, unregister them from MachineDebugInfo.
if (MDI && !MBB->empty()) {
- unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
- assert(DWARF_LABELOpc &&
- "Target supports dwarf but didn't implement getDWARF_LABELOpcode!");
-
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
- if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
+ if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
// The label ID # is always operand #0, an immediate.
MDI->InvalidateLabel(I->getOperand(0).getImm());
}
// Get target instruction info.
const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
if (!TII) return false;
- // Get target version of the debug label opcode.
- unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
- if (!DWARF_LABELOpc) return false;
// Track if change is made.
bool MadeChange = false;
// Iterate through instructions.
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) {
// Is it a debug label.
- if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
+ if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
// The label ID # is always operand #0, an immediate.
unsigned NextLabel = I->getOperand(0).getImm();
case TargetLowering::Expand: {
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
- bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
+ bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
- if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
+ if (DebugInfo && (useDEBUG_LOC || useLABEL)) {
const std::string &FName =
cast<StringSDNode>(Node->getOperand(3))->getValue();
const std::string &DirName =
unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
Ops.push_back(DAG.getConstant(ID, MVT::i32));
- Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
+ Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
}
} else {
Result = Tmp1; // chain
}
break;
- case ISD::DEBUG_LABEL:
- assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
- switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
+ case ISD::LABEL:
+ assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
+ switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
+ case ISD::LABEL:
break;
case ISD::CopyToReg: {
unsigned InReg;
case ISD::UNDEF: return "undef";
case ISD::MERGE_VALUES: return "mergevalues";
case ISD::INLINEASM: return "inlineasm";
+ case ISD::LABEL: return "label";
case ISD::HANDLENODE: return "handlenode";
case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
case ISD::CALL: return "call";
// Debug info
case ISD::LOCATION: return "location";
case ISD::DEBUG_LOC: return "debug_loc";
- case ISD::DEBUG_LABEL: return "debug_label";
case ISD::CONDCODE:
switch (cast<CondCodeSDNode>(this)->get()) {
DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
DAG.getConstant(LabelID, MVT::i32)));
}
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
if (DebugInfo && FSI.getSubprogram() &&
DebugInfo->Verify(FSI.getSubprogram())) {
unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
// If this machine instr is an inline asm, measure it.
if (MI->getOpcode() == ARM::INLINEASM)
return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
+ if (MI->getOpcode() == ARM::LABEL)
+ return 0;
assert(0 && "Unknown or unset size field for instr!");
break;
case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (Subtarget->isTargetDarwin())
- setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::LABEL, MVT::Other, Expand);
setOperationAction(ISD::RET, MVT::Other, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
RI(*this, STI) {
}
-unsigned ARMInstrInfo::getDWARF_LABELOpcode() const {
- return ARM::DWARF_LABEL;
-}
-
const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
return &ARM::GPRRegClass;
}
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
- /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
- /// instruction if it has one. This is used by codegen passes that update
- /// DWARF line number info as they modify the code.
- virtual unsigned getDWARF_LABELOpcode() const;
-
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
".loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
-def DWARF_LABEL :
-PseudoInst<(ops i32imm:$id),
- "\nLdebug_loc${id:no_hash}:",
- [(dwarf_label (i32 imm:$id))]>;
-
def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp),
"\n$cp:\n\tadd $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::LABEL, MVT::Other, Expand);
// Not implemented yet.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::LABEL, MVT::Other, Expand);
//IA64 has these, but they are not implemented
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
const char *AsmStr = MI->getOperand(0).getSymbolName();
return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
}
+ case PPC::LABEL: {
+ return 0;
+ }
default:
return 4; // PowerPC instructions are all 4 bytes
}
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
- setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::LABEL, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
- /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
- /// instruction if it has one. This is used by codegen passes that update
- /// DWARF line number info as they modify the code.
- virtual unsigned getDWARF_LABELOpcode() const {
- return PPC::DWARF_LABEL;
- }
-
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
//
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
-def DWARF_LABEL : Pseudo<(ops i32imm:$id),
- "\n${:private}debug_loc$id:",
- [(dwarf_label (i32 imm:$id))]>;
-
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
//
if (hasInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = DebugInfo->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer: r1 += NegFrameSize.
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = DebugInfo->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::LABEL, MVT::Other, Expand);
// RET must be custom lowered, to meet ABI requirements
setOperationAction(ISD::RET , MVT::Other, Custom);
let AsmString = "";
let Namespace = "TargetInstrInfo";
}
+def LABEL : Instruction {
+ let OperandList = (ops i32imm:$id);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let hasCtrlDep = 1;
+}
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
-def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
-def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;
-
assert(0 && "psuedo instructions should be removed before code emission");
case TargetInstrInfo::INLINEASM:
assert(0 && "JIT does not support inline asm!\n");
+ case TargetInstrInfo::LABEL:
+ assert(0 && "JIT does not support meta labels!\n");
case X86::IMPLICIT_USE:
case X86::IMPLICIT_DEF:
case X86::IMPLICIT_DEF_GR8:
if (!Subtarget->isTargetDarwin() &&
!Subtarget->isTargetELF() &&
!Subtarget->isTargetCygMing())
- setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::LABEL, MVT::Other, Expand);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);
TM(tm), RI(tm, *this) {
}
-/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
-/// instruction if it has one. This is used by codegen passes that update
-/// DWARF line number info as they modify the code.
-unsigned X86InstrInfo::getDWARF_LABELOpcode() const {
- return X86::DWARF_LABEL;
-}
-
-
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
- /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
- /// instruction if it has one. This is used by codegen passes that update
- /// DWARF line number info as they modify the code.
- virtual unsigned getDWARF_LABELOpcode() const;
-
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
/// may be able to convert a two-address instruction into a true
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
-def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
- "\n${:private}debug_loc${id:debug}:",
- [(dwarf_label (i32 imm:$id))]>;
-
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
if (hasInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = DebugInfo->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
}
if (hasFP(MF)) {
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = DebugInfo->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
MachineLocation FPSrc(MachineLocation::VirtualFP);
projects / oota-llvm.git / commitdiff