ARM: S5PV310: Limit the irqs which support cascade interrupt

The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the
interrupt combiner. This patch limits the irqs which should be initialized
to support cascade interrupt.

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 82ce4aa6d61a5c07f004f26cc08e11d80f583b0d..3d0c1cb68d9ed061f512dfc39c1858728b7e7d64 100644 (file)
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -127,6 +127,15 @@ void __init s5pv310_init_irq(void)
        gic_cpu_init(0, S5P_VA_GIC_CPU);
 
        for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+
+               /*
+                * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
+                * connected to the interrupt combiner. These irqs
+                * should be initialized to support cascade interrupt.
+                */
+               if ((irq >= 40) && !(irq == 51) && !(irq == 53))
+                       continue;
+
                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
                                COMBINER_IRQ(irq, 0));
                combiner_cascade_irq(irq, IRQ_SPI(irq));