Merge tag 'v3.19-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git...

Merge "first bunch on Rockchip dt changes" from Heiko Stübner:

First hunk of rockchip devicetree patches, containing:
- cpu operating points and supplies
- dma support for spi controllers
- i2s on rk3066 and rk3188
- default core clock settings for rk3288

* tag 'v3.19-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Add SPI DMA into rk3288.dtsi
  ARM: dts: rockchip: enable init rate for clock
  ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188
  ARM: dts: rockchip: enable DMA on SPI for rk3066 and rk3188
  ARM: dts: rockchip: add cpu supplies to boards
  ARM: dts: rockchip: add operating points and armclk references

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index d5344510c6763f3dbd2b74c0c71593db213fdbdd..baf21ac6ce7f5a2116e65bc9439a87326597a284 100644 (file)
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -60,6 +60,10 @@
        };
 };
 
+&cpu0 {
+       cpu0-supply = <&vdd_arm>;
+};
+
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ad9c2db59670659a9142edfbe486459f0eb84f35..0e99470db772415cd2275620380858903fa41320 100644 (file)
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
                #size-cells = <0>;
                enable-method = "rockchip,rk3066-smp";
 
-               cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1008000 1075000
+                                816000 1025000
+                                600000 1025000
+                                504000 1000000
+                                312000  975000
+                       >;
+                       clock-latency = <40000>;
+                       clocks = <&cru ARMCLK>;
                };
                cpu@1 {
                        device_type = "cpu";
@@ -53,6 +63,51 @@
                };
        };
 
+       i2s0: i2s@10118000 {
+               compatible = "rockchip,rk3066-i2s";
+               reg = <0x10118000 0x2000>;
+               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s0_bus>;
+               dmas = <&dmac1_s 4>, <&dmac1_s 5>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_hclk", "i2s_clk";
+               clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+               status = "disabled";
+       };
+
+       i2s1: i2s@1011a000 {
+               compatible = "rockchip,rk3066-i2s";
+               reg = <0x1011a000 0x2000>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s1_bus>;
+               dmas = <&dmac1_s 6>, <&dmac1_s 7>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_hclk", "i2s_clk";
+               clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
+               status = "disabled";
+       };
+
+       i2s2: i2s@1011c000 {
+               compatible = "rockchip,rk3066-i2s";
+               reg = <0x1011c000 0x2000>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s2_bus>;
+               dmas = <&dmac1_s 9>, <&dmac1_s 10>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_hclk", "i2s_clk";
+               clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
+               status = "disabled";
+       };
+
        cru: clock-controller@20000000 {
                compatible = "rockchip,rk3066a-cru";
                reg = <0x20000000 0x1000>;
@@ -405,6 +460,42 @@
                                                <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
                        };
                };
+
+               i2s0 {
+                       i2s0_bus: i2s0-bus {
+                               rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
+                       };
+               };
+
+               i2s1 {
+                       i2s1_bus: i2s1-bus {
+                               rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
+                       };
+               };
+
+               i2s2 {
+                       i2s2_bus: i2s2-bus {
+                               rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
+                                               <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
+                       };
+               };
        };
 };
 

diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 15910c9ddbc7c6cb33c30904a4107b387693e132..0950a052494703dd28e8f568d4f9c85764c0c30f 100644 (file)
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -118,6 +118,10 @@
        };
 };
 
+&cpu0 {
+       cpu0-supply = <&vdd_arm>;
+};
+
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
@@ -159,7 +163,7 @@
                        vdd_arm: REG3 {
                                regulator-name = "VDD_ARM";
                                regulator-min-microvolt = <875000>;
-                               regulator-max-microvolt = <1300000>;
+                               regulator-max-microvolt = <1350000>;
                                regulator-always-on;
                        };
 

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ddaada788b4584429840953311cd806a7c2cff19..b24e04f6ccc77031d8ab8d096775956bff2e0a3f 100644 (file)
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,11 +26,24 @@
                #size-cells = <0>;
                enable-method = "rockchip,rk3066-smp";
 
-               cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1608000 1350000
+                               1416000 1250000
+                               1200000 1150000
+                               1008000 1075000
+                                816000  975000
+                                600000  950000
+                                504000  925000
+                                312000  875000
+                       >;
+                       clock-latency = <40000>;
+                       clocks = <&cru ARMCLK>;
                };
                cpu@1 {
                        device_type = "cpu";
@@ -65,6 +78,21 @@
                };
        };
 
+       i2s0: i2s@1011a000 {
+               compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
+               reg = <0x1011a000 0x2000>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s0_bus>;
+               dmas = <&dmac1_s 6>, <&dmac1_s 7>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_hclk", "i2s_clk";
+               clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+               status = "disabled";
+       };
+
        cru: clock-controller@20000000 {
                compatible = "rockchip,rk3188-cru";
                reg = <0x20000000 0x1000>;
@@ -395,6 +423,17 @@
                                                <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
                        };
                };
+
+               i2s0 {
+                       i2s0_bus: i2s0-bus {
+                               rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
+                                               <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
+                                               <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
+                                               <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
+                                               <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
+                                               <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
        };
 };
 

diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index ff522f8e3df4ea393a00a83b509f4452b1ef1bff..d8c775e6d5fe7d7ca73a3142b5c8b5707797b7cb 100644 (file)
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -17,6 +17,10 @@
        compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
 };
 
+&cpu0 {
+       cpu0-supply = <&vdd_cpu>;
+};
+
 &i2c0 {
        clock-frequency = <400000>;
        status = "okay";
@@ -44,7 +48,7 @@
                                regulator-always-on;
                                regulator-boot-on;
                                regulator-min-microvolt = <750000>;
-                               regulator-max-microvolt = <1300000>;
+                               regulator-max-microvolt = <1350000>;
                                regulator-name = "vdd_arm";
                        };
 

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66dbb93be117c5ff7afda004d8151b3603fd..cfc43789cac68f3449beb4db84a6366ff19441f3 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -47,10 +47,27 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@500 {
+               cpu0: cpu@500 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x500>;
+                       operating-points = <
+                               /* KHz    uV */
+                               1608000 1350000
+                               1512000 1300000
+                               1416000 1200000
+                               1200000 1100000
+                               1008000 1050000
+                                816000 1000000
+                                696000  950000
+                                600000  900000
+                                408000  900000
+                                312000  900000
+                                216000  900000
+                                126000  900000
+                       >;
+                       clock-latency = <40000>;
+                       clocks = <&cru ARMCLK>;
                };
                cpu@501 {
                        device_type = "cpu";
@@ -177,6 +194,8 @@
                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
                clock-names = "spiclk", "apb_pclk";
+               dmas = <&dmac_peri 11>, <&dmac_peri 12>;
+               dma-names = "tx", "rx";
                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
@@ -190,6 +209,8 @@
                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
                clock-names = "spiclk", "apb_pclk";
+               dmas = <&dmac_peri 13>, <&dmac_peri 14>;
+               dma-names = "tx", "rx";
                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
@@ -203,6 +224,8 @@
                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
                clock-names = "spiclk", "apb_pclk";
+               dmas = <&dmac_peri 15>, <&dmac_peri 16>;
+               dma-names = "tx", "rx";
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
@@ -455,6 +478,16 @@
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
+               assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+                                 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+                                 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+                                 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+                                 <&cru PCLK_PERI>;
+               assigned-clock-rates = <594000000>, <400000000>,
+                                      <500000000>, <300000000>,
+                                      <150000000>, <75000000>,
+                                      <300000000>, <150000000>,
+                                      <75000000>;
        };
 
        grf: syscon@ff770000 {

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 499468d42adac51007f6c663c6b2e0e64cd67ef6..9ba92de511cae32fa156d445973c508a89edf52e 100644 (file)
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -367,6 +367,8 @@
                reg = <0x20070000 0x1000>;
                #address-cells = <1>;
                #size-cells = <0>;
+               dmas = <&dmac2 10>, <&dmac2 11>;
+               dma-names = "tx", "rx";
                status = "disabled";
        };
 
@@ -378,6 +380,8 @@
                reg = <0x20074000 0x1000>;
                #address-cells = <1>;
                #size-cells = <0>;
+               dmas = <&dmac2 12>, <&dmac2 13>;
+               dma-names = "tx", "rx";
                status = "disabled";
        };
 };