rk29: clock: add set rate for aclk_periph/hclk_periph/pclk_periph
author黄涛 <huangtao@rock-chips.com>
Sat, 4 Dec 2010 08:30:32 +0000 (16:30 +0800)
committer黄涛 <huangtao@rock-chips.com>
Sat, 4 Dec 2010 08:31:07 +0000 (16:31 +0800)
arch/arm/mach-rk29/clock.c

index bd4735e1ec08870320e58c154a97256eb54bb479..202d83a6dac07404f09d7f062642dabfbe2f3f8a 100755 (executable)
@@ -545,6 +545,7 @@ static struct clk hclk_cpu = {
        .name           = "hclk_cpu",
        .parent         = &aclk_cpu,
        .recalc         = clksel_recalc_shift,
+       .set_rate       = clksel_set_rate_shift,
        .clksel_con     = CRU_CLKSEL0_CON,
        .clksel_mask    = 3,
        .clksel_shift   = 8,
@@ -555,6 +556,7 @@ static struct clk pclk_cpu = {
        .name           = "pclk_cpu",
        .parent         = &aclk_cpu,
        .recalc         = clksel_recalc_shift,
+       .set_rate       = clksel_set_rate_shift,
        .clksel_con     = CRU_CLKSEL0_CON,
        .clksel_mask    = 3,
        .clksel_shift   = 10,
@@ -567,6 +569,7 @@ static struct clk aclk_periph = {
        .gate_idx       = CLK_GATE_PEIRPH_AXI,
        .parent         = &periph_pll_clk,
        .recalc         = clksel_recalc_div,
+       .set_rate       = clksel_set_rate_div,
        .clksel_con     = CRU_CLKSEL0_CON,
        .clksel_mask    = 0x1F,
        .clksel_shift   = 14,
@@ -578,6 +581,7 @@ static struct clk pclk_periph = {
        .gate_idx       = CLK_GATE_PEIRPH_APB,
        .parent         = &aclk_periph,
        .recalc         = clksel_recalc_shift,
+       .set_rate       = clksel_set_rate_shift,
        .clksel_con     = CRU_CLKSEL0_CON,
        .clksel_mask    = 3,
        .clksel_shift   = 19,
@@ -590,6 +594,7 @@ static struct clk hclk_periph = {
        .gate_idx       = CLK_GATE_PEIRPH_AHB,
        .parent         = &aclk_periph,
        .recalc         = clksel_recalc_shift,
+       .set_rate       = clksel_set_rate_shift,
        .clksel_con     = CRU_CLKSEL0_CON,
        .clksel_mask    = 3,
        .clksel_shift   = 21,