.name = "hclk_cpu",
.parent = &aclk_cpu,
.recalc = clksel_recalc_shift,
+ .set_rate = clksel_set_rate_shift,
.clksel_con = CRU_CLKSEL0_CON,
.clksel_mask = 3,
.clksel_shift = 8,
.name = "pclk_cpu",
.parent = &aclk_cpu,
.recalc = clksel_recalc_shift,
+ .set_rate = clksel_set_rate_shift,
.clksel_con = CRU_CLKSEL0_CON,
.clksel_mask = 3,
.clksel_shift = 10,
.gate_idx = CLK_GATE_PEIRPH_AXI,
.parent = &periph_pll_clk,
.recalc = clksel_recalc_div,
+ .set_rate = clksel_set_rate_div,
.clksel_con = CRU_CLKSEL0_CON,
.clksel_mask = 0x1F,
.clksel_shift = 14,
.gate_idx = CLK_GATE_PEIRPH_APB,
.parent = &aclk_periph,
.recalc = clksel_recalc_shift,
+ .set_rate = clksel_set_rate_shift,
.clksel_con = CRU_CLKSEL0_CON,
.clksel_mask = 3,
.clksel_shift = 19,
.gate_idx = CLK_GATE_PEIRPH_AHB,
.parent = &aclk_periph,
.recalc = clksel_recalc_shift,
+ .set_rate = clksel_set_rate_shift,
.clksel_con = CRU_CLKSEL0_CON,
.clksel_mask = 3,
.clksel_shift = 21,