Summary:
This patch consists of the suggestions of clang-tidy/misc-static-assert check.
Reviewers: alexfh
Reviewed By: alexfh
Subscribers: xazax.hun, llvm-commits
Differential Revision: http://reviews.llvm.org/D8343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232366
91177308-0d34-0410-b5e6-
96231b3b80d8
if (!isUInt<5>(MI->getOperand(1).getImm()))
report("Unknown asm flags", &MI->getOperand(1), 1);
- assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed");
+ static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
unsigned OpNo = InlineAsm::MIOp_FirstOperand;
unsigned NumOps;
void SlotIndexes::renumberIndexes(IndexList::iterator curItr) {
// Number indexes with half the default spacing so we can catch up quickly.
const unsigned Space = SlotIndex::InstrDist/2;
- assert((Space & 3) == 0 && "InstrDist must be a multiple of 2*NUM");
+ static_assert((Space & 3) == 0, "InstrDist must be a multiple of 2*NUM");
IndexList::iterator startItr = std::prev(curItr);
unsigned index = startItr->getIndex();
0, // length of DW_LNS_set_epilogue_begin
1 // DW_LNS_set_isa
};
- assert(array_lengthof(StandardOpcodeLengths) == (DWARF2_LINE_OPCODE_BASE - 1));
+ static_assert(array_lengthof(StandardOpcodeLengths) ==
+ (DWARF2_LINE_OPCODE_BASE - 1),
+ "");
return Emit(MCOS, StandardOpcodeLengths);
}
// Otherwise do it the hard way.
// To be compatible with above bulk transfer, we need to take endianness
// into account.
+ static_assert(sys::IsBigEndianHost || sys::IsLittleEndianHost,
+ "Unexpected host endianness");
if (sys::IsBigEndianHost) {
for (Pos += 4; Pos <= Size; Pos += 4) {
unsigned V = ((unsigned char)String[Pos - 4] << 24) |
(unsigned char)String[Pos - 1];
Bits.push_back(V);
}
- } else {
- assert(sys::IsLittleEndianHost && "Unexpected host endianness");
+ } else { // Little-endian host
for (Pos += 4; Pos <= Size; Pos += 4) {
unsigned V = ((unsigned char)String[Pos - 1] << 24) |
((unsigned char)String[Pos - 2] << 16) |
// function. If it is all integer, there is nothing for us to do!
bool FPIsUsed = false;
- assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
+ static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
for (unsigned i = 0; i <= 6; ++i)
if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
FPIsUsed = true;
// 9 ) EFLAGS (implicit-def)
assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
- assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
+ static_assert(X86::AddrNumOperands == 5,
+ "VAARG_64 assumes 5 address operands");
unsigned DestReg = MI->getOperand(0).getReg();
MachineOperand &Base = MI->getOperand(1);
void FunctionStackPoisoner::SetShadowToStackAfterReturnInlined(
IRBuilder<> &IRB, Value *ShadowBase, int Size) {
assert(!(Size % 8));
- assert(kAsanStackAfterReturnMagic == 0xf5);
+
+ #ifndef NDEBUG
+ static_assert(kAsanStackAfterReturnMagic == 0xf5, "");
+ #endif
+
for (int i = 0; i < Size; i += 8) {
Value *p = IRB.CreateAdd(ShadowBase, ConstantInt::get(IntptrTy, i));
IRB.CreateStore(ConstantInt::get(IRB.getInt64Ty(), 0xf5f5f5f5f5f5f5f5ULL),
typedef Graph<NUM_NODES> GT;
/// Enumerate all graphs using NUM_GRAPHS bits.
- assert(NUM_GRAPHS < sizeof(unsigned) * CHAR_BIT && "Too many graphs!");
+ static_assert(NUM_GRAPHS < sizeof(unsigned) * CHAR_BIT, "Too many graphs!");
for (unsigned GraphDescriptor = 0; GraphDescriptor < (1U << NUM_GRAPHS);
++GraphDescriptor) {
GT G;