#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/power/rk3288-power.h>
+#include <dt-bindings/power/rk3366-power.h>
#include <dt-bindings/power/rk3368-power.h>
struct rockchip_domain_info {
[RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2),
};
+static const struct rockchip_domain_info rk3366_pm_domains[] = {
+ [RK3366_PD_PERI] = DOMAIN_RK3368(10, 10, 6),
+ [RK3366_PD_VIO] = DOMAIN_RK3368(14, 14, 8),
+ [RK3366_PD_VIDEO] = DOMAIN_RK3368(13, 13, 7),
+ [RK3366_PD_RKVDEC] = DOMAIN_RK3368(11, 11, 7),
+ [RK3366_PD_WIFIBT] = DOMAIN_RK3368(8, 8, 9),
+ [RK3366_PD_VPU] = DOMAIN_RK3368(12, 12, 7),
+ [RK3366_PD_GPU] = DOMAIN_RK3368(15, 15, 2),
+};
+
static const struct rockchip_domain_info rk3368_pm_domains[] = {
[RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6),
[RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8),
.domain_info = rk3288_pm_domains,
};
+static const struct rockchip_pmu_info rk3366_pmu = {
+ .pwr_offset = 0x0c,
+ .status_offset = 0x10,
+ .req_offset = 0x3c,
+ .idle_offset = 0x40,
+ .ack_offset = 0x40,
+
+ .core_pwrcnt_offset = 0x48,
+ .gpu_pwrcnt_offset = 0x50,
+
+ .core_power_transition_time = 24,
+ .gpu_power_transition_time = 24,
+
+ .num_domains = ARRAY_SIZE(rk3366_pm_domains),
+ .domain_info = rk3366_pm_domains,
+};
+
static const struct rockchip_pmu_info rk3368_pmu = {
.pwr_offset = 0x0c,
.status_offset = 0x10,
.compatible = "rockchip,rk3288-power-controller",
.data = (void *)&rk3288_pmu,
},
+ {
+ .compatible = "rockchip,rk3366-power-controller",
+ .data = (void *)&rk3366_pmu,
+ },
{
.compatible = "rockchip,rk3368-power-controller",
.data = (void *)&rk3368_pmu,