Add a new scheduling type. This is, of course, a hack. Proper factoring

will come later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26551 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 5bc51e8582f5fd04b20c6ce6c987ccd18b59e130..b99e429ab1244f8cd2be35bc3503f371b3ff6776 100644 (file)
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -34,17 +34,16 @@ namespace llvm {
   typedef std::vector<NodeInfoPtr>           NIVector;
   typedef std::vector<NodeInfoPtr>::iterator NIIterator;
 
-
   // Scheduling heuristics
   enum SchedHeuristics {
     defaultScheduling,      // Let the target specify its preference.
     noScheduling,           // No scheduling, emit breath first sequence.
     simpleScheduling,       // Two pass, min. critical path, max. utilization.
     simpleNoItinScheduling, // Same as above exact using generic latency.
-    listSchedulingBURR      // Bottom up reg reduction list scheduling.
+    listSchedulingBURR,     // Bottom up reg reduction list scheduling.
+    listSchedulingG5        // G5-specific scheduler. FIXME: parameterize better
   };
 
-
   //===--------------------------------------------------------------------===//
   ///
   /// Node group -  This struct is used to manage flagged node groups.
@@ -359,6 +358,12 @@ namespace llvm {
   /// reduction list scheduler.
   ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
                                           MachineBasicBlock *BB);
+  
+  /// createTDG5ListDAGScheduler - This creates a top-down list scheduler for
+  /// the PowerPC G5.  FIXME: pull the priority function out into the PPC
+  /// backend!
+  ScheduleDAG* createTDG5ListDAGScheduler(SelectionDAG &DAG,
+                                          MachineBasicBlock *BB);
 }
 
 #endif