Don't depend on the physreg coalescing order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130818 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/x86-64-extend-shift.ll b/test/CodeGen/X86/x86-64-extend-shift.ll
index 6852785fd6afff50f5f98edce4970022d1472c48..6ebaeee36697135bac5b54340fbb39f5d6a340b5 100644 (file)
--- a/test/CodeGen/X86/x86-64-extend-shift.ll
+++ b/test/CodeGen/X86/x86-64-extend-shift.ll
@@ -2,7 +2,7 @@
 ; Formerly there were two shifts.
 
 define i64 @baz(i32 %A) nounwind {
-; CHECK:  shlq  $49, %rax
+; CHECK:  shlq  $49, %r
         %tmp1 = shl i32 %A, 17
         %tmp2 = zext i32 %tmp1 to i64
         %tmp3 = shl i64 %tmp2, 32

diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index b90d81ac9b18867eb2d9752ab496c23718cfbc97..178c59dbaa97bd949101c814690452471cc238ba 100644 (file)
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -29,9 +29,8 @@ entry:
         ret i32 %tmp4
         
 ; X64: test3:
-; X64: notl    [[A1:%esi|%edx]]
-; X64: andl    [[A0:%edi|%ecx]], [[A1]]
-; X64: movl    [[A1]], %eax
+; X64: notl
+; X64: andl
 ; X64: shrl    %eax
 ; X64: ret
 
@@ -139,7 +138,7 @@ entry:
   %t2 = add i32 %t1, -1
   ret i32 %t2
 ; X64: test8:
-; X64:   notl %eax
+; X64:   notl {{%eax|%edi|%ecx}}
 ; X32: test8:
 ; X32:   notl %eax
 }