Add support for 64-bit arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24792 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index a2eb9c7acb9d4f995f7edef74b3cb14ed4b6d0e9..a17637a46ab11178c0be6b320e0e3da4aa71a36f 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -102,6 +102,18 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
       }
       ArgValues.push_back(Arg);
+      break;
+    }
+    case MVT::i64: {
+      unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+      MF.addLiveIn(GPR[ArgNo++], VRegLo);
+      unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+      MF.addLiveIn(GPR[ArgNo++], VRegHi);
+      SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
+      SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
+      DAG.setRoot(ArgHi.getValue(1));
+      ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
+      break;
     }
     }
   }

diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index a2eb9c7acb9d4f995f7edef74b3cb14ed4b6d0e9..a17637a46ab11178c0be6b320e0e3da4aa71a36f 100644 (file)
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -102,6 +102,18 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
       }
       ArgValues.push_back(Arg);
+      break;
+    }
+    case MVT::i64: {
+      unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+      MF.addLiveIn(GPR[ArgNo++], VRegLo);
+      unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+      MF.addLiveIn(GPR[ArgNo++], VRegHi);
+      SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
+      SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
+      DAG.setRoot(ArgHi.getValue(1));
+      ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
+      break;
     }
     }
   }