#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
+#ifdef CONFIG_USB_ANDROID
+#include <linux/usb/android_composite.h>
+#endif
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <asm/pmu.h>
#endif
platform_device_register(&device_pcm);
}
+#ifdef CONFIG_USB20_OTG
+/*DWC_OTG*/
+static struct resource usb20_otg_resource[] = {
+ {
+ .start = IRQ_USB_OTG,
+ .end = IRQ_USB_OTG,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK30_USBOTG20_PHYS,
+ .end = RK30_USBOTG20_PHYS + RK30_USBOTG20_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+
+};
+
+struct platform_device device_usb20_otg = {
+ .name = "usb20_otg",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(usb20_otg_resource),
+ .resource = usb20_otg_resource,
+};
+#endif
+#ifdef CONFIG_USB20_HOST
+static struct resource usb20_host_resource[] = {
+ {
+ .start = IRQ_USB_HOST,
+ .end = IRQ_USB_HOST,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK30_USBHOST20_PHYS,
+ .end = RK30_USBHOST20_PHYS + RK30_USBHOST20_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+
+};
+
+struct platform_device device_usb20_host = {
+ .name = "usb20_host",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(usb20_host_resource),
+ .resource = usb20_host_resource,
+};
+#endif
#ifdef CONFIG_KEYS_RK29
extern struct rk29_keys_platform_data rk29_keys_pdata;
#ifdef CONFIG_KEYS_RK29
platform_device_register(&device_keys);
#endif
+#ifdef CONFIG_USB20_OTG
+ platform_device_register(&device_usb20_otg);
+#endif
+#ifdef CONFIG_USB20_HOST
+ platform_device_register(&device_usb20_host);
+#endif
#ifdef CONFIG_RGA_RK30
platform_device_register(&device_rga);
#endif
void dump_scu_regs(void)
{
+#ifdef CONFIG_ARCH_RK29
int regvalue;
DWC_PRINT("_______________________System Regs________________________________\n");
regvalue = dwc_read_reg32((uint32_t *)(SCU_BASE_ADDR_VA+0x00));
DWC_PRINT("USB_PHY_CON1: 0x%08x\n",regvalue);
regvalue = dwc_read_reg32((uint32_t *)(USB_GRF_IOMUX));
DWC_PRINT("GRF_GPIO4L_IOMUX: 0x%08x\n",regvalue);
+#endif
}
void dwc_otg_dump_flags(dwc_otg_core_if_t *_core_if)
{
#include "dwc_otg_cil.h"
#include "dwc_otg_pcd.h"
#include "dwc_otg_hcd.h"
-
+#ifdef CONFIG_ARCH_RK29
#include <mach/cru.h>
-
+#endif
//#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006"
//#define DWC_DRIVER_VERSION "2.70 2009-12-31"
#define DWC_DRIVER_VERSION "3.00 2010-12-12 rockchip"
int irq;
int32_t regval;
struct clk *ahbclk,*phyclk,*busclk;
+#ifdef CONFIG_ARCH_RK29
unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
-
+#endif
+#ifdef CONFIG_ARCH_RK30
+ unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON2);
+#endif
regval = * otg_phy_con1;
+#ifdef CONFIG_ARCH_RK29
#ifndef CONFIG_USB11_HOST
/*
* disable usb host 1.1 controller if not support
clk_disable(phyclk);
clk_disable(ahbclk);
#endif
-
- #if 0
- otgreg = ioremap(RK2818_USBOTG_PHYS,RK2818_USBOTG_SIZE);
- DWC_PRINT("otgreg 0x%x",otgreg);
- dwc_modify_reg32((uint32_t *)(otgreg+0xc),0x20000000,0x20000000);
- dwc_write_reg32((uint32_t *)(otgreg+0x440), 0x1000);
- #endif
+#endif
dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
dwc_otg_device->reg_offset = 0xFFFFFFFF;
+#ifdef CONFIG_ARCH_RK29
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, true);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, true);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_CONTROLLER, true);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, false);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, false);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_CONTROLLER, false);
-
busclk = clk_get(NULL, "hclk_usb_peri");
if (IS_ERR(busclk)) {
retval = PTR_ERR(busclk);
dwc_otg_device->phyclk = phyclk;
dwc_otg_device->ahbclk = ahbclk;
dwc_otg_device->busclk = busclk;
+#endif
/*
* Map the DWC_otg Core memory into virtual address space.
*/
/* Initialize the bus state. If the core is in Device Mode
* HALT the USB bus and return. */
#ifndef CONFIG_DWC_OTG_DEVICE_ONLY
+#ifdef CONFIG_ARCH_RK29
USB_IOMUX_INIT(GPIO4A5_OTG0DRVVBUS_NAME, GPIO4L_OTG0_DRV_VBUS);
+#endif
+#ifdef CONFIG_ARCH_RK30
+ USB_IOMUX_INIT(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A_OTG_DRV_VBUS);
+#endif
/*
* Initialize the HCD
*/
* handlers are installed.
*/
dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
+#ifdef CONFIG_ARCH_RK29
#ifndef CONFIG_DWC_OTG_DEVICE_ONLY
if(dwc_otg_device->hcd->host_enabled == 0)
{
*otg_phy_con1 |= (0x01<<2);
*otg_phy_con1 &= ~(0x01<<3); // enter suspend.
}
+#endif
#endif
return 0;
fail:
rk28_usb_suspend(0);
del_timer(&otg_dev->pcd->check_vbus_timer);
- //DWC_PRINT("CRU_CLKGATE1_CON: 0x%08x\n",dwc_read_reg32((uint32_t *)(SCU_BASE_ADDR_VA+0x60)));
- //DWC_PRINT("USB_PHY_CON1: 0x%08x\n",dwc_read_reg32((uint32_t *)(USB_GRF_CON)));
return 0;
}
#else
/*
*Enable usb phy
*/
+#ifdef CONFIG_ARCH_RK29
unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
+#endif
+#ifdef CONFIG_ARCH_RK30
+ unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON2);
+#endif
otgreg = * otg_phy_con1;
otgreg |= (0x01<<13); // software control
dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
+#ifdef CONFIG_ARCH_RK29
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_AHB_BUS, true);
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_PHY, true);
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_CONTROLLER, true);
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_AHB_BUS, false);
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_PHY, false);
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_CONTROLLER, false);
-
+#endif
if (dwc_otg_device == 0)
{
dev_err(dev, "kmalloc of dwc_otg_device failed\n");
}
clk_enable(phyclk);
+#ifdef CONFIG_ARCH_RK29
ahbclk = clk_get(NULL, "usbotg1");
+#endif
+#ifdef CONFIG_ARCH_RK30
+ ahbclk = clk_get(NULL, "hclk_otg1");
+#endif
if (IS_ERR(ahbclk)) {
retval = PTR_ERR(ahbclk);
DWC_ERROR("can't get USBOTG1 ahb bus clock\n");
{
dwc_otg_device->common_irq_installed = 1;
}
-
+
+#ifdef CONFIG_ARCH_RK29
USB_IOMUX_INIT(GPIO4A6_OTG1DRVVBUS_NAME, GPIO4L_OTG1_DRV_VBUS);
+#endif
+#ifdef CONFIG_ARCH_RK30
+ USB_IOMUX_INIT(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A_HOST_DRV_VBUS);
+#endif
/*
* Initialize the DWC_otg core.
*/
*/
static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
{
+#ifdef CONFIG_ARCH_RK29
unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
if(suspend) {
*otg_phy_con1 &= ~(0x01<<3); // enter suspend.
DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
}
-
+#endif
return suspend;
}
/* Initialize the DWC OTG HCD. */
dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-
- spin_lock_init(&dwc_otg_hcd->global_lock);
-
dwc_otg_hcd->core_if = otg_dev->core_if;
otg_dev->hcd = dwc_otg_hcd;
dwc_otg_hcd->host_enabled = 0;
#endif
- spin_lock_init(&dwc_otg_hcd->global_lock);
-
/* Register the HCD CIL Callbacks */
dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
goto error3;
}
-// DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
-// dev->bus_id, hcd->self.busnum);
+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
+ _lmdev->dev.bus_id, hcd->self.busnum);
return 0;
*/
static int32_t host20_phy_suspend_cb( void *_p, int suspend)
{
+#ifdef CONFIG_ARCH_RK29
unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
uint32_t regval;
DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
}
*otg_phy_con1 = regval;
-
+#endif
return suspend;
}
dwc_otg_hcd->host_enabled = 0;
#endif
- spin_lock_init(&dwc_otg_hcd->global_lock);
-
/* Register the HCD CIL Callbacks */
dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
{
dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
- unsigned long flags;
struct usb_bus *bus;
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
- spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
bus = hcd_to_bus(_hcd);
_hcd->state = HC_STATE_RUNNING;
}
hcd_reinit(dwc_otg_hcd);
out:
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
return 0;
}
int retval;
dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
dwc_otg_qtd_t * qtd;
- unsigned long flags;
#if 0
retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
if (retval)
return retval;
}
#endif
- spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
#if 1
/*
* Make sure the start of frame interrupt is enabled now that
dwc_otg_hcd_qtd_free(qtd);
}
out:
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
return retval;
}
//int retval;
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
+ local_irq_save(flags);
urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
if(_ep==NULL)
{
return -1;
}
qh = (dwc_otg_qh_t *) _ep->hcpriv;
- spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
- #if 0
- retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
- if (retval) {
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
- return retval;
- }
- #endif
if(urb_qtd == NULL)
{
DWC_PRINT("%s,urb_qtd is null\n",__func__);
}
#endif /* */
-#if 1
+
if (urb_qtd == qh->qtd_in_process) {
/* The QTD is in process (it has been assigned to a channel). */
if (dwc_otg_hcd->flags.b.port_connect_status) {
} else if (list_empty(&qh->qtd_list)) {
dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
}
-#endif
+ local_irq_restore(flags);
urb_qtd_null:
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
_urb->hcpriv = NULL;
//usb_hcd_unlink_urb_from_ep(_hcd, _urb);
/* Higher layer software sets URB status. */
struct usb_host_endpoint *_ep)
{
- unsigned long flags;
dwc_otg_qh_t *qh;
dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
- spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
-
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
"endpoint=%d\n", _ep->desc.bEndpointAddress,
dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
_ep->hcpriv = NULL;
}
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
-
return;
}
* This function is called by the USB core when an interrupt occurs */
irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
{
- irqreturn_t result;
- unsigned long flags;
dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
-
- spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
-
- result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
-
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
-
- return result;
+ return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
}
/** Creates Status Change bitmap for the root hub and root port. The bitmap is
u16 _wLength)
{
int retval = 0;
- unsigned long flags;
dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
hprt0_data_t hprt0 = {.d32 = 0};
uint32_t port_status;
- spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
switch (_typeReq) {
case ClearHubFeature:
hprt0.b.prtrst = 1;
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
}
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
// kever @rk 20110712
// can not use mdelay(60) while irq disable
//MDELAY (60);
msleep(60);
- spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
hprt0.b.prtrst = 0;
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
break;
break;
}
- spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
return retval;
}
}
#endif
-
+ _urb->status = _status;
_urb->hcpriv = NULL;
- //usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
- spin_unlock(&_hcd->lock);
usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
- spin_lock(&_hcd->lock);
}
void dwc_otg_clear_halt(struct urb *_urb)
/* Tasket to do a reset */
struct tasklet_struct *reset_tasklet;
- spinlock_t global_lock;
-
#ifdef DEBUG
uint32_t frrem_samples;
uint64_t frrem_accum;
* non-periodic transactions.
*/
int status;
-#if 0
+#ifdef CONFIG_ARCH_RK30
int num_channels;
num_channels = _hcd->core_if->core_params->host_channels;
*/
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
+ unsigned long flags;
int status = 0;
- if (!spin_is_locked(&_hcd->global_lock)) {
- //pr_err("%s don't have hcd->global_lock\n", __func__);
- //BUG();
- }
+ local_irq_save(flags);
if (!list_empty(&_qh->qh_list_entry)) {
/* QH already in a schedule. */
}
done:
- //local_irq_restore(flags);
+ local_irq_restore(flags);
return status;
}
* @param[in] _qh QH to remove from schedule. */
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
{
- if (!spin_is_locked(&_hcd->global_lock)) {
- //pr_err("%s don't have hcd->global_lock\n", __func__);
- //BUG();
- }
+ unsigned long flags;
+
+ local_irq_save(flags);
if (list_empty(&_qh->qh_list_entry)) {
/* QH is not in a schedule. */
}
done:
- ;
+ local_irq_restore(flags);
}
/**
*/
void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
{
- if (!spin_is_locked(&_hcd->global_lock)) {
- //pr_err("%s don't have hcd->global_lock\n", __func__);
- //BUG();
- }
+ unsigned long flags;
+ local_irq_save(flags);
+
if (dwc_qh_is_non_per(_qh)) {
dwc_otg_hcd_qh_remove(_hcd, _qh);
if (!list_empty(&_qh->qtd_list)) {
}
}
-
+ local_irq_restore(flags);
}
/**
{
struct usb_host_endpoint *ep;
dwc_otg_qh_t *qh;
- //unsigned long flags;
+ unsigned long flags;
int retval = 0;
struct urb *urb = _qtd->urb;
- //local_irq_save(flags);
/*
* Get the QH which holds the QTD-list to insert to. Create QH if it
}
ep->hcpriv = qh;
}
-
+
+ local_irq_save(flags);
retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
if (retval == 0) {
list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
}
done:
- //local_irq_restore(flags);
+ local_irq_restore(flags);
return retval;
}
#include "dwc_otg_regs.h"
#include <linux/usb/composite.h>
+#ifdef CONFIG_ARCH_RK29
#include <mach/cru.h>
-
+#endif
/**
* Static PCD pointer for use in usb_gadget_register_driver and
* usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
pcd = ep->pcd;
if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN)
{
- DWC_WARN("%s, bogus device state\n", __func__);
+ DWC_WARN("%s, bogus device state, %p, speed %d\n", __func__, pcd->driver, pcd->gadget.speed);
return -ESHUTDOWN;
}
//#endif
if (pcd->driver && pcd->driver->resume)
{
- SPIN_UNLOCK(&pcd->lock);
+// SPIN_UNLOCK(&pcd->lock);
pcd->driver->suspend(&pcd->gadget);
- SPIN_LOCK(&pcd->lock);
+// SPIN_LOCK(&pcd->lock);
}
return 1;
}
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
dwc_otg_disable_global_interrupts( core_if );
//
-
+#ifdef CONFIG_ARCH_RK29
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, true);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, true);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_CONTROLLER, true);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, false);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, false);
cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_CONTROLLER, false);
-
+#endif
//rockchip_scu_reset_unit(12);
dwc_otg_pcd_reinit( pcd );
dwc_otg_core_dev_init(core_if);
int rk28_usb_suspend( int exitsuspend )
{
dwc_otg_pcd_t *pcd = s_pcd;
-
+#ifdef CONFIG_ARCH_RK29
unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
+#endif
+#ifdef CONFIG_ARCH_RK30
+ unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON2);
+#endif
if(exitsuspend && (pcd->phy_suspend == 1)) {
clk_enable(pcd->otg_dev->ahbclk);
clk_enable(pcd->otg_dev->phyclk);
memset( pcd, 0, sizeof(dwc_otg_pcd_t));
spin_lock_init( &pcd->lock );
-
+ spin_lock(&pcd->lock);
otg_dev->pcd = pcd;
s_pcd = pcd;
pcd->gadget.name = pcd_name;
//strcpy(pcd->gadget.dev.bus_id, "gadget");
+ spin_unlock(&pcd->lock);
pcd->otg_dev = otg_dev;
pcd->gadget.dev.parent = dev;
pcd->vbus_status = 0;
pcd->phy_suspend = 0;
if(dwc_otg_is_device_mode(core_if))
- mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<4)); // delay 16 S
+ mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<2)); // delay 16 S +(HZ<<4)
+ DWC_PRINT("%s pass,everest\n", __func__);
// dwc_otg_pcd_start_vbus_timer( pcd );
return 0;
}
/* report disconnect; the driver is already quiesced */
if (_pcd->driver && _pcd->driver->disconnect)
{
- SPIN_UNLOCK(&_pcd->lock);
+// SPIN_UNLOCK(&_pcd->lock);
_pcd->driver->disconnect(&_pcd->gadget);
- SPIN_LOCK(&_pcd->lock);
+// SPIN_LOCK(&_pcd->lock);
}
}
struct usb_ctrlrequest *ctrl = &_pcd->setup_pkt->req;
DWC_WARN("req %02x.%02x v%04x i%04x l%04x protocol STALL; err %d\n",
ctrl->bRequestType, ctrl->bRequest,ctrl->wValue, ctrl->wIndex, ctrl->wLength, err_val);
- dump_stack();
ep0->dwc_ep.is_in = 1;
dwc_otg_ep_set_stall( _pcd->otg_dev->core_if, &ep0->dwc_ep );
#include <linux/list.h>
#include <linux/delay.h>
#include <asm/io.h>
-
+#ifdef CONFIG_ARCH_RK29
#include <mach/rk29_iomap.h>
#include <mach/iomux.h>
#define GRF_REG_BASE RK29_GRF_BASE
#define SCU_BASE_ADDR_VA RK29_CRU_BASE
#endif
#define USB_IOMUX_INIT(a,b) rk29_mux_api_set(a,b)
+#endif
+
+#ifdef CONFIG_ARCH_RK30
+#include <mach/iomux.h>
+#define GRF_REG_BASE RK30_GRF_BASE
+#define USBOTG_SIZE RK30_USBOTG20_SIZE
+#define USBGRF_UOC0_CON2 (GRF_REG_BASE+0x184)
+#define USBGRF_UOC1_CON2 (GRF_REG_BASE+0x190)
+#define USB_IOMUX_INIT(a,b) rk30_mux_api_set(a,b)
+#endif
+
/**
* @file
*
projects / firefly-linux-kernel-4.4.55.git / commitdiff