expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31014 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 13dd33cc9028ded045029613ff9cf0aab27e7ec3..72d25c8dcf68345b86ddc2dfa5d345641c673559 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -75,6 +75,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+  setOperationAction(ISD::SDIV,      MVT::i32, Expand);
+  setOperationAction(ISD::UDIV,      MVT::i32, Expand);
+  setOperationAction(ISD::SREM,      MVT::i32, Expand);
+  setOperationAction(ISD::UREM,      MVT::i32, Expand);
 
   setOperationAction(ISD::VASTART,       MVT::Other, Custom);
   setOperationAction(ISD::VAEND,         MVT::Other, Expand);

diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll
new file mode 100644 (file)
index 0000000..1d78394
--- /dev/null
+++ b/test/CodeGen/ARM/div.ll
@@ -0,0 +1,29 @@
+; RUN: llvm-as < %s | llc -march=arm &&
+; RUN: llvm-as < %s | llc -march=arm | grep __divsi3  &&
+; RUN: llvm-as < %s | llc -march=arm | grep __udivsi3 &&
+; RUN: llvm-as < %s | llc -march=arm | grep __modsi3  &&
+; RUN: llvm-as < %s | llc -march=arm | grep __umodsi3
+
+int %f1(int %a, int %b) {
+entry:
+       %tmp1 = div int %a, %b
+       ret int %tmp1
+}
+
+uint %f2(uint %a, uint %b) {
+entry:
+       %tmp1 = div uint %a, %b
+       ret uint %tmp1
+}
+
+int %f3(int %a, int %b) {
+entry:
+       %tmp1 = rem int %a, %b
+       ret int %tmp1
+}
+
+uint %f4(uint %a, uint %b) {
+entry:
+       %tmp1 = rem uint %a, %b
+       ret uint %tmp1
+}