clk: rk3288: modify RK3288_LIMIT_PLL_VIO0/1

This commit corresponds to commit debf1d2237185a26503d737d54db730f62cf5ea5.

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 3417e27769b0357b7551f35f53d4ddfe908272c3..7107134a8e7e56de6f684af95577d04b8e19c945 100644 (file)
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -558,7 +558,7 @@ const struct clk_ops clkops_rate_3288_usb480m = {
        .recalc_rate    = clk_3288_usb480m_recalc_rate,
 };
 
-#define RK3288_LIMIT_PLL_VIO0 (400*MHZ)
+#define RK3288_LIMIT_PLL_VIO0 (410*MHZ)
 
 static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long rate,
                unsigned long *best_parent_rate,
@@ -619,7 +619,7 @@ const struct clk_ops clkops_rate_3288_dclk_lcdc0 = {
        .recalc_rate    = clk_divider_recalc_rate,
 };
 
-#define RK3288_LIMIT_PLL_VIO1 (410*MHZ)
+#define RK3288_LIMIT_PLL_VIO1 (350*MHZ)
 
 static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long rate,
                unsigned long *best_parent_rate,