drm/radeon: implement clock and power gating for CIK (v3)
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 23 Jul 2013 13:41:05 +0000 (09:41 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:08 +0000 (16:30 -0400)
Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cik.c
drivers/gpu/drm/radeon/cikd.h
drivers/gpu/drm/radeon/clearstate_ci.h [new file with mode: 0644]
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/si.c

index 8389917af9a220436b53464ca462dbdfdbd197d9..a36e98c9a8751e40196d43cc0826fc8ed7bc24d8 100644 (file)
@@ -31,6 +31,7 @@
 #include "atom.h"
 #include "cik_blit_shaders.h"
 #include "radeon_ucode.h"
+#include "clearstate_ci.h"
 
 MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
 MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
@@ -61,9 +62,12 @@ extern void sumo_rlc_fini(struct radeon_device *rdev);
 extern int sumo_rlc_init(struct radeon_device *rdev);
 extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 extern void si_rlc_reset(struct radeon_device *rdev);
+extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
 static void cik_rlc_stop(struct radeon_device *rdev);
 static void cik_pcie_gen3_enable(struct radeon_device *rdev);
 static void cik_program_aspm(struct radeon_device *rdev);
+static void cik_init_pg(struct radeon_device *rdev);
+static void cik_init_cg(struct radeon_device *rdev);
 
 /*
  * Indirect registers accessor
@@ -86,6 +90,778 @@ void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
        (void)RREG32(PCIE_DATA);
 }
 
+static const u32 spectre_rlc_save_restore_register_list[] =
+{
+       (0x0e00 << 16) | (0xc12c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc140 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc150 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc15c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc168 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc170 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc178 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc204 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2b8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2bc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2c0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8228 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x829c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x869c >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x98f4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x98f8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9900 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc260 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x90e8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c000 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c00c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c1c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9700 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x8e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x9e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0xae00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0xbe00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x89bc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8900 >> 2),
+       0x00000000,
+       0x3,
+       (0x0e00 << 16) | (0xc130 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc134 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc1fc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc208 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc264 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc268 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc26c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc270 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc274 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc278 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc27c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc280 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc284 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc288 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc28c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc290 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc294 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc298 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc29c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2a0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2a4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2a8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2ac  >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2b0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x301d0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30238 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30250 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30254 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30258 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3025c >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x8e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x9e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0xae00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0xbe00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x8e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x9e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0xae00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0xbe00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x8e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x9e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0xae00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0xbe00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x8e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x9e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0xae00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0xbe00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x8e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x9e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0xae00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0xbe00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc99c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9834 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f00 >> 2),
+       0x00000000,
+       (0x0001 << 16) | (0x30f00 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f04 >> 2),
+       0x00000000,
+       (0x0001 << 16) | (0x30f04 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f08 >> 2),
+       0x00000000,
+       (0x0001 << 16) | (0x30f08 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f0c >> 2),
+       0x00000000,
+       (0x0001 << 16) | (0x30f0c >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x9b7c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8a14 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8a18 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a00 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8bf0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8bcc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8b24 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30a04 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a10 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a14 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a18 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a2c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc700 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc704 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc708 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc768 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc770 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc774 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc778 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc77c >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc780 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc784 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc788 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc78c >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc798 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc79c >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc7a0 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc7a4 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc7a8 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc7ac >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc7b0 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc7b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9100 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c010 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92a8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92ac >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92b8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92bc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92c0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92c4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92c8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92cc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x92d0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c00 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c04 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c20 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c38 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c3c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xae00 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9604 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac08 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac0c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac10 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac14 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac58 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac68 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac6c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac70 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac74 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac78 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac7c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac80 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac84 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac88 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac8c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x970c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9714 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9718 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x971c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x8e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x9e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0xae00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0xbe00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xcd10 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xcd14 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88b0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88b8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88bc >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0x89c0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88c4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88c8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88d0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88d4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88d8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8980 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30938 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3093c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30940 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x89a0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30900 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30904 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x89b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c210 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c214 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c218 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8904 >> 2),
+       0x00000000,
+       0x5,
+       (0x0e00 << 16) | (0x8c28 >> 2),
+       (0x0e00 << 16) | (0x8c2c >> 2),
+       (0x0e00 << 16) | (0x8c30 >> 2),
+       (0x0e00 << 16) | (0x8c34 >> 2),
+       (0x0e00 << 16) | (0x9600 >> 2),
+};
+
+static const u32 kalindi_rlc_save_restore_register_list[] =
+{
+       (0x0e00 << 16) | (0xc12c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc140 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc150 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc15c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc168 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc170 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc204 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2b8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2bc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2c0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8228 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x829c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x869c >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x98f4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x98f8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9900 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc260 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x90e8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c000 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c00c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c1c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9700 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xcd20 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x89bc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8900 >> 2),
+       0x00000000,
+       0x3,
+       (0x0e00 << 16) | (0xc130 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc134 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc1fc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc208 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc264 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc268 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc26c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc270 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc274 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc28c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc290 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc294 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc298 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2a0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2a4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2a8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc2ac >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x301d0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30238 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30250 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30254 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30258 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3025c >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc900 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc904 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc908 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc90c >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0xc910 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc99c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9834 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f00 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f04 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f08 >> 2),
+       0x00000000,
+       (0x0000 << 16) | (0x30f0c >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x9b7c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8a14 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8a18 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a00 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8bf0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8bcc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8b24 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30a04 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a10 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a14 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a18 >> 2),
+       0x00000000,
+       (0x0600 << 16) | (0x30a2c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc700 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc704 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc708 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xc768 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc770 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc774 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc798 >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0xc79c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9100 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c010 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c00 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c04 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c20 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c38 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8c3c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xae00 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9604 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac08 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac0c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac10 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac14 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac58 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac68 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac6c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac70 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac74 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac78 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac7c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac80 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac84 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac88 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xac8c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x970c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9714 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x9718 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x971c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x4e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x5e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x6e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x7e00 << 16) | (0x31068 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xcd10 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0xcd14 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88b0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88b8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88bc >> 2),
+       0x00000000,
+       (0x0400 << 16) | (0x89c0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88c4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88c8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88d0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88d4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x88d8 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8980 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30938 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3093c >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30940 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x89a0 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30900 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x30904 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x89b4 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3e1fc >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c210 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c214 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x3c218 >> 2),
+       0x00000000,
+       (0x0e00 << 16) | (0x8904 >> 2),
+       0x00000000,
+       0x5,
+       (0x0e00 << 16) | (0x8c28 >> 2),
+       (0x0e00 << 16) | (0x8c2c >> 2),
+       (0x0e00 << 16) | (0x8c30 >> 2),
+       (0x0e00 << 16) | (0x8c34 >> 2),
+       (0x0e00 << 16) | (0x9600 >> 2),
+};
+
 static const u32 bonaire_golden_spm_registers[] =
 {
        0x30800, 0xe0ffffff, 0xe0000000
@@ -4778,6 +5554,39 @@ static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
        }
 }
 
+static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
+{
+       u32 tmp;
+
+       tmp = RREG32(RLC_CNTL);
+       if (tmp != rlc)
+               WREG32(RLC_CNTL, rlc);
+}
+
+static u32 cik_halt_rlc(struct radeon_device *rdev)
+{
+       u32 data, orig;
+
+       orig = data = RREG32(RLC_CNTL);
+
+       if (data & RLC_ENABLE) {
+               u32 i;
+
+               data &= ~RLC_ENABLE;
+               WREG32(RLC_CNTL, data);
+
+               for (i = 0; i < rdev->usec_timeout; i++) {
+                       if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
+                               break;
+                       udelay(1);
+               }
+
+               cik_wait_for_rlc_serdes(rdev);
+       }
+
+       return orig;
+}
+
 /**
  * cik_rlc_stop - stop the RLC ME
  *
@@ -4787,20 +5596,10 @@ static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
  */
 static void cik_rlc_stop(struct radeon_device *rdev)
 {
-       u32 tmp;
+       WREG32(RLC_CNTL, 0);
 
        cik_enable_gui_idle_interrupt(rdev, false);
 
-       RREG32(CB_CGTT_SCLK_CTRL);
-       RREG32(CB_CGTT_SCLK_CTRL);
-       RREG32(CB_CGTT_SCLK_CTRL);
-       RREG32(CB_CGTT_SCLK_CTRL);
-
-       tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
-       WREG32(RLC_CGCG_CGLS_CTRL, tmp);
-
-       WREG32(RLC_CNTL, 0);
-
        cik_wait_for_rlc_serdes(rdev);
 }
 
@@ -4831,8 +5630,7 @@ static void cik_rlc_start(struct radeon_device *rdev)
  */
 static int cik_rlc_resume(struct radeon_device *rdev)
 {
-       u32 i, size;
-       u32 clear_state_info[3];
+       u32 i, size, tmp;
        const __be32 *fw_data;
 
        if (!rdev->rlc_fw)
@@ -4853,8 +5651,16 @@ static int cik_rlc_resume(struct radeon_device *rdev)
 
        cik_rlc_stop(rdev);
 
+       /* disable CG */
+       tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
+       WREG32(RLC_CGCG_CGLS_CTRL, tmp);
+
        si_rlc_reset(rdev);
 
+       cik_init_pg(rdev);
+
+       cik_init_cg(rdev);
+
        WREG32(RLC_LB_CNTR_INIT, 0);
        WREG32(RLC_LB_CNTR_MAX, 0x00008000);
 
@@ -4875,20 +5681,634 @@ static int cik_rlc_resume(struct radeon_device *rdev)
        /* XXX - find out what chips support lbpw */
        cik_enable_lbpw(rdev, false);
 
-       /* XXX */
-       clear_state_info[0] = 0;//upper_32_bits(rdev->rlc.save_restore_gpu_addr);
-       clear_state_info[1] = 0;//rdev->rlc.save_restore_gpu_addr;
-       clear_state_info[2] = 0;//cik_default_size;
-       WREG32(RLC_GPM_SCRATCH_ADDR, 0x3d);
-       for (i = 0; i < 3; i++)
-               WREG32(RLC_GPM_SCRATCH_DATA, clear_state_info[i]);
-       WREG32(RLC_DRIVER_DMA_STATUS, 0);
+       if (rdev->family == CHIP_BONAIRE)
+               WREG32(RLC_DRIVER_DMA_STATUS, 0);
 
        cik_rlc_start(rdev);
 
        return 0;
 }
 
+static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
+{
+       u32 data, orig, tmp, tmp2;
+
+       orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
+
+       cik_enable_gui_idle_interrupt(rdev, enable);
+
+       if (enable) {
+               tmp = cik_halt_rlc(rdev);
+
+               cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
+               WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
+               WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
+               tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
+               WREG32(RLC_SERDES_WR_CTRL, tmp2);
+
+               cik_update_rlc(rdev, tmp);
+
+               data |= CGCG_EN | CGLS_EN;
+       } else {
+               RREG32(CB_CGTT_SCLK_CTRL);
+               RREG32(CB_CGTT_SCLK_CTRL);
+               RREG32(CB_CGTT_SCLK_CTRL);
+               RREG32(CB_CGTT_SCLK_CTRL);
+
+               data &= ~(CGCG_EN | CGLS_EN);
+       }
+
+       if (orig != data)
+               WREG32(RLC_CGCG_CGLS_CTRL, data);
+
+}
+
+static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
+{
+       u32 data, orig, tmp = 0;
+
+       if (enable) {
+               orig = data = RREG32(CP_MEM_SLP_CNTL);
+               data |= CP_MEM_LS_EN;
+               if (orig != data)
+                       WREG32(CP_MEM_SLP_CNTL, data);
+
+               orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
+               data &= 0xfffffffd;
+               if (orig != data)
+                       WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
+
+               tmp = cik_halt_rlc(rdev);
+
+               cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
+               WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
+               WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
+               data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
+               WREG32(RLC_SERDES_WR_CTRL, data);
+
+               cik_update_rlc(rdev, tmp);
+
+               orig = data = RREG32(CGTS_SM_CTRL_REG);
+               data &= ~SM_MODE_MASK;
+               data |= SM_MODE(0x2);
+               data |= SM_MODE_ENABLE;
+               data &= ~CGTS_OVERRIDE;
+               data &= ~CGTS_LS_OVERRIDE;
+               data &= ~ON_MONITOR_ADD_MASK;
+               data |= ON_MONITOR_ADD_EN;
+               data |= ON_MONITOR_ADD(0x96);
+               if (orig != data)
+                       WREG32(CGTS_SM_CTRL_REG, data);
+       } else {
+               orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
+               data |= 0x00000002;
+               if (orig != data)
+                       WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
+
+               data = RREG32(RLC_MEM_SLP_CNTL);
+               if (data & RLC_MEM_LS_EN) {
+                       data &= ~RLC_MEM_LS_EN;
+                       WREG32(RLC_MEM_SLP_CNTL, data);
+               }
+
+               data = RREG32(CP_MEM_SLP_CNTL);
+               if (data & CP_MEM_LS_EN) {
+                       data &= ~CP_MEM_LS_EN;
+                       WREG32(CP_MEM_SLP_CNTL, data);
+               }
+
+               orig = data = RREG32(CGTS_SM_CTRL_REG);
+               data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
+               if (orig != data)
+                       WREG32(CGTS_SM_CTRL_REG, data);
+
+               tmp = cik_halt_rlc(rdev);
+
+               cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
+               WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
+               WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
+               data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
+               WREG32(RLC_SERDES_WR_CTRL, data);
+
+               cik_update_rlc(rdev, tmp);
+       }
+}
+
+static const u32 mc_cg_registers[] =
+{
+       MC_HUB_MISC_HUB_CG,
+       MC_HUB_MISC_SIP_CG,
+       MC_HUB_MISC_VM_CG,
+       MC_XPB_CLK_GAT,
+       ATC_MISC_CG,
+       MC_CITF_MISC_WR_CG,
+       MC_CITF_MISC_RD_CG,
+       MC_CITF_MISC_VM_CG,
+       VM_L2_CG,
+};
+
+static void cik_enable_mc_ls(struct radeon_device *rdev,
+                            bool enable)
+{
+       int i;
+       u32 orig, data;
+
+       for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
+               orig = data = RREG32(mc_cg_registers[i]);
+               if (enable)
+                       data |= MC_LS_ENABLE;
+               else
+                       data &= ~MC_LS_ENABLE;
+               if (data != orig)
+                       WREG32(mc_cg_registers[i], data);
+       }
+}
+
+static void cik_enable_mc_mgcg(struct radeon_device *rdev,
+                              bool enable)
+{
+       int i;
+       u32 orig, data;
+
+       for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
+               orig = data = RREG32(mc_cg_registers[i]);
+               if (enable)
+                       data |= MC_CG_ENABLE;
+               else
+                       data &= ~MC_CG_ENABLE;
+               if (data != orig)
+                       WREG32(mc_cg_registers[i], data);
+       }
+}
+
+static void cik_enable_sdma_mgcg(struct radeon_device *rdev,
+                                bool enable)
+{
+       u32 orig, data;
+
+       if (enable) {
+               WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
+               WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
+       } else {
+               orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
+               data |= 0xff000000;
+               if (data != orig)
+                       WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
+
+               orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
+               data |= 0xff000000;
+               if (data != orig)
+                       WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
+       }
+}
+
+static void cik_enable_sdma_mgls(struct radeon_device *rdev,
+                                bool enable)
+{
+       u32 orig, data;
+
+       if (enable) {
+               orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
+               data |= 0x100;
+               if (orig != data)
+                       WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
+
+               orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
+               data |= 0x100;
+               if (orig != data)
+                       WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
+       } else {
+               orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
+               data &= ~0x100;
+               if (orig != data)
+                       WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
+
+               orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
+               data &= ~0x100;
+               if (orig != data)
+                       WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
+       }
+}
+
+static void cik_enable_uvd_mgcg(struct radeon_device *rdev,
+                               bool enable)
+{
+       u32 orig, data;
+
+       if (enable) {
+               data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
+               data = 0xfff;
+               WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
+
+               orig = data = RREG32(UVD_CGC_CTRL);
+               data |= DCM;
+               if (orig != data)
+                       WREG32(UVD_CGC_CTRL, data);
+       } else {
+               data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
+               data &= ~0xfff;
+               WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
+
+               orig = data = RREG32(UVD_CGC_CTRL);
+               data &= ~DCM;
+               if (orig != data)
+                       WREG32(UVD_CGC_CTRL, data);
+       }
+}
+
+static void cik_enable_hdp_mgcg(struct radeon_device *rdev,
+                               bool enable)
+{
+       u32 orig, data;
+
+       orig = data = RREG32(HDP_HOST_PATH_CNTL);
+
+       if (enable)
+               data &= ~CLOCK_GATING_DIS;
+       else
+               data |= CLOCK_GATING_DIS;
+
+       if (orig != data)
+               WREG32(HDP_HOST_PATH_CNTL, data);
+}
+
+static void cik_enable_hdp_ls(struct radeon_device *rdev,
+                             bool enable)
+{
+       u32 orig, data;
+
+       orig = data = RREG32(HDP_MEM_POWER_LS);
+
+       if (enable)
+               data |= HDP_LS_ENABLE;
+       else
+               data &= ~HDP_LS_ENABLE;
+
+       if (orig != data)
+               WREG32(HDP_MEM_POWER_LS, data);
+}
+
+void cik_update_cg(struct radeon_device *rdev,
+                  u32 block, bool enable)
+{
+       if (block & RADEON_CG_BLOCK_GFX) {
+               /* order matters! */
+               if (enable) {
+                       cik_enable_mgcg(rdev, true);
+                       cik_enable_cgcg(rdev, true);
+               } else {
+                       cik_enable_cgcg(rdev, false);
+                       cik_enable_mgcg(rdev, false);
+               }
+       }
+
+       if (block & RADEON_CG_BLOCK_MC) {
+               if (!(rdev->flags & RADEON_IS_IGP)) {
+                       cik_enable_mc_mgcg(rdev, enable);
+                       cik_enable_mc_ls(rdev, enable);
+               }
+       }
+
+       if (block & RADEON_CG_BLOCK_SDMA) {
+               cik_enable_sdma_mgcg(rdev, enable);
+               cik_enable_sdma_mgls(rdev, enable);
+       }
+
+       if (block & RADEON_CG_BLOCK_UVD) {
+               if (rdev->has_uvd)
+                       cik_enable_uvd_mgcg(rdev, enable);
+       }
+
+       if (block & RADEON_CG_BLOCK_HDP) {
+               cik_enable_hdp_mgcg(rdev, enable);
+               cik_enable_hdp_ls(rdev, enable);
+       }
+}
+
+static void cik_init_cg(struct radeon_device *rdev)
+{
+
+       cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, false); /* XXX true */
+
+       if (rdev->has_uvd)
+               si_init_uvd_internal_cg(rdev);
+
+       cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
+                            RADEON_CG_BLOCK_SDMA |
+                            RADEON_CG_BLOCK_UVD |
+                            RADEON_CG_BLOCK_HDP), true);
+}
+
+static void cik_enable_sck_slowdown_on_pu(struct radeon_device *rdev,
+                                         bool enable)
+{
+       u32 data, orig;
+
+       orig = data = RREG32(RLC_PG_CNTL);
+       if (enable)
+               data |= SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
+       else
+               data &= ~SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
+       if (orig != data)
+               WREG32(RLC_PG_CNTL, data);
+}
+
+static void cik_enable_sck_slowdown_on_pd(struct radeon_device *rdev,
+                                         bool enable)
+{
+       u32 data, orig;
+
+       orig = data = RREG32(RLC_PG_CNTL);
+       if (enable)
+               data |= SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
+       else
+               data &= ~SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
+       if (orig != data)
+               WREG32(RLC_PG_CNTL, data);
+}
+
+static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
+{
+       u32 data, orig;
+
+       orig = data = RREG32(RLC_PG_CNTL);
+       if (enable)
+               data &= ~DISABLE_CP_PG;
+       else
+               data |= DISABLE_CP_PG;
+       if (orig != data)
+               WREG32(RLC_PG_CNTL, data);
+}
+
+static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
+{
+       u32 data, orig;
+
+       orig = data = RREG32(RLC_PG_CNTL);
+       if (enable)
+               data &= ~DISABLE_GDS_PG;
+       else
+               data |= DISABLE_GDS_PG;
+       if (orig != data)
+               WREG32(RLC_PG_CNTL, data);
+}
+
+#define CP_ME_TABLE_SIZE    96
+#define CP_ME_TABLE_OFFSET  2048
+#define CP_MEC_TABLE_OFFSET 4096
+
+void cik_init_cp_pg_table(struct radeon_device *rdev)
+{
+       const __be32 *fw_data;
+       volatile u32 *dst_ptr;
+       int me, i, max_me = 4;
+       u32 bo_offset = 0;
+       u32 table_offset;
+
+       if (rdev->family == CHIP_KAVERI)
+               max_me = 5;
+
+       if (rdev->rlc.cp_table_ptr == NULL)
+               return;
+
+       /* write the cp table buffer */
+       dst_ptr = rdev->rlc.cp_table_ptr;
+       for (me = 0; me < max_me; me++) {
+               if (me == 0) {
+                       fw_data = (const __be32 *)rdev->ce_fw->data;
+                       table_offset = CP_ME_TABLE_OFFSET;
+               } else if (me == 1) {
+                       fw_data = (const __be32 *)rdev->pfp_fw->data;
+                       table_offset = CP_ME_TABLE_OFFSET;
+               } else if (me == 2) {
+                       fw_data = (const __be32 *)rdev->me_fw->data;
+                       table_offset = CP_ME_TABLE_OFFSET;
+               } else {
+                       fw_data = (const __be32 *)rdev->mec_fw->data;
+                       table_offset = CP_MEC_TABLE_OFFSET;
+               }
+
+               for (i = 0; i < CP_ME_TABLE_SIZE; i ++) {
+                       dst_ptr[bo_offset + i] = be32_to_cpu(fw_data[table_offset + i]);
+               }
+               bo_offset += CP_ME_TABLE_SIZE;
+       }
+}
+
+static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
+                               bool enable)
+{
+       u32 data, orig;
+
+       if (enable) {
+               orig = data = RREG32(RLC_PG_CNTL);
+               data |= GFX_PG_ENABLE;
+               if (orig != data)
+                       WREG32(RLC_PG_CNTL, data);
+
+               orig = data = RREG32(RLC_AUTO_PG_CTRL);
+               data |= AUTO_PG_EN;
+               if (orig != data)
+                       WREG32(RLC_AUTO_PG_CTRL, data);
+       } else {
+               orig = data = RREG32(RLC_PG_CNTL);
+               data &= ~GFX_PG_ENABLE;
+               if (orig != data)
+                       WREG32(RLC_PG_CNTL, data);
+
+               orig = data = RREG32(RLC_AUTO_PG_CTRL);
+               data &= ~AUTO_PG_EN;
+               if (orig != data)
+                       WREG32(RLC_AUTO_PG_CTRL, data);
+
+               data = RREG32(DB_RENDER_CONTROL);
+       }
+}
+
+static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
+{
+       u32 mask = 0, tmp, tmp1;
+       int i;
+
+       cik_select_se_sh(rdev, se, sh);
+       tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
+       tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
+       cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
+
+       tmp &= 0xffff0000;
+
+       tmp |= tmp1;
+       tmp >>= 16;
+
+       for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
+               mask <<= 1;
+               mask |= 1;
+       }
+
+       return (~tmp) & mask;
+}
+
+static void cik_init_ao_cu_mask(struct radeon_device *rdev)
+{
+       u32 i, j, k, active_cu_number = 0;
+       u32 mask, counter, cu_bitmap;
+       u32 tmp = 0;
+
+       for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
+               for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
+                       mask = 1;
+                       cu_bitmap = 0;
+                       counter = 0;
+                       for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
+                               if (cik_get_cu_active_bitmap(rdev, i, j) & mask) {
+                                       if (counter < 2)
+                                               cu_bitmap |= mask;
+                                       counter ++;
+                               }
+                               mask <<= 1;
+                       }
+
+                       active_cu_number += counter;
+                       tmp |= (cu_bitmap << (i * 16 + j * 8));
+               }
+       }
+
+       WREG32(RLC_PG_AO_CU_MASK, tmp);
+
+       tmp = RREG32(RLC_MAX_PG_CU);
+       tmp &= ~MAX_PU_CU_MASK;
+       tmp |= MAX_PU_CU(active_cu_number);
+       WREG32(RLC_MAX_PG_CU, tmp);
+}
+
+static void cik_enable_gfx_static_mgpg(struct radeon_device *rdev,
+                                      bool enable)
+{
+       u32 data, orig;
+
+       orig = data = RREG32(RLC_PG_CNTL);
+       if (enable)
+               data |= STATIC_PER_CU_PG_ENABLE;
+       else
+               data &= ~STATIC_PER_CU_PG_ENABLE;
+       if (orig != data)
+               WREG32(RLC_PG_CNTL, data);
+}
+
+static void cik_enable_gfx_dynamic_mgpg(struct radeon_device *rdev,
+                                       bool enable)
+{
+       u32 data, orig;
+
+       orig = data = RREG32(RLC_PG_CNTL);
+       if (enable)
+               data |= DYN_PER_CU_PG_ENABLE;
+       else
+               data &= ~DYN_PER_CU_PG_ENABLE;
+       if (orig != data)
+               WREG32(RLC_PG_CNTL, data);
+}
+
+#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
+#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
+
+static void cik_init_gfx_cgpg(struct radeon_device *rdev)
+{
+       u32 data, orig;
+       u32 i;
+
+       if (rdev->rlc.cs_data) {
+               WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
+               WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
+               WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_gpu_addr);
+               WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
+       } else {
+               WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
+               for (i = 0; i < 3; i++)
+                       WREG32(RLC_GPM_SCRATCH_DATA, 0);
+       }
+       if (rdev->rlc.reg_list) {
+               WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
+               for (i = 0; i < rdev->rlc.reg_list_size; i++)
+                       WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
+       }
+
+       orig = data = RREG32(RLC_PG_CNTL);
+       data |= GFX_PG_SRC;
+       if (orig != data)
+               WREG32(RLC_PG_CNTL, data);
+
+       WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
+       WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
+
+       data = RREG32(CP_RB_WPTR_POLL_CNTL);
+       data &= ~IDLE_POLL_COUNT_MASK;
+       data |= IDLE_POLL_COUNT(0x60);
+       WREG32(CP_RB_WPTR_POLL_CNTL, data);
+
+       data = 0x10101010;
+       WREG32(RLC_PG_DELAY, data);
+
+       data = RREG32(RLC_PG_DELAY_2);
+       data &= ~0xff;
+       data |= 0x3;
+       WREG32(RLC_PG_DELAY_2, data);
+
+       data = RREG32(RLC_AUTO_PG_CTRL);
+       data &= ~GRBM_REG_SGIT_MASK;
+       data |= GRBM_REG_SGIT(0x700);
+       WREG32(RLC_AUTO_PG_CTRL, data);
+
+}
+
+static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
+{
+       bool has_pg = false;
+       bool has_dyn_mgpg = false;
+       bool has_static_mgpg = false;
+
+       /* only APUs have PG */
+       if (rdev->flags & RADEON_IS_IGP) {
+               has_pg = true;
+               has_static_mgpg = true;
+               if (rdev->family == CHIP_KAVERI)
+                       has_dyn_mgpg = true;
+       }
+
+       if (has_pg) {
+               cik_enable_gfx_cgpg(rdev, enable);
+               if (enable) {
+                       cik_enable_gfx_static_mgpg(rdev, has_static_mgpg);
+                       cik_enable_gfx_dynamic_mgpg(rdev, has_dyn_mgpg);
+               } else {
+                       cik_enable_gfx_static_mgpg(rdev, false);
+                       cik_enable_gfx_dynamic_mgpg(rdev, false);
+               }
+       }
+
+}
+
+void cik_init_pg(struct radeon_device *rdev)
+{
+       bool has_pg = false;
+
+       /* only APUs have PG */
+       if (rdev->flags & RADEON_IS_IGP) {
+               /* XXX disable this for now */
+               /* has_pg = true; */
+       }
+
+       if (has_pg) {
+               cik_enable_sck_slowdown_on_pu(rdev, true);
+               cik_enable_sck_slowdown_on_pd(rdev, true);
+               cik_init_gfx_cgpg(rdev);
+               cik_enable_cp_pg(rdev, true);
+               cik_enable_gds_pg(rdev, true);
+               cik_init_ao_cu_mask(rdev);
+               cik_update_gfx_pg(rdev, true);
+       }
+}
+
 /*
  * Interrupts
  * Starting with r6xx, interrupts are handled via a ring buffer.
@@ -6019,6 +7439,19 @@ static int cik_startup(struct radeon_device *rdev)
        cik_gpu_init(rdev);
 
        /* allocate rlc buffers */
+       if (rdev->flags & RADEON_IS_IGP) {
+               if (rdev->family == CHIP_KAVERI) {
+                       rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
+                       rdev->rlc.reg_list_size =
+                               (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
+               } else {
+                       rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
+                       rdev->rlc.reg_list_size =
+                               (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
+               }
+       }
+       rdev->rlc.cs_data = ci_cs_data;
+       rdev->rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
        r = sumo_rlc_init(rdev);
        if (r) {
                DRM_ERROR("Failed to init rlc BOs!\n");
index 4742f3db4aa68f31e69b00e1f5c507896fe7c6df..63955abb1e11cf8624ba20e3f9216836a0685143 100644 (file)
 #define        VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
 #define        VM_CONTEXT1_PAGE_TABLE_END_ADDR                 0x1580
 
+#define VM_L2_CG                                       0x15c0
+#define                MC_CG_ENABLE                            (1 << 18)
+#define                MC_LS_ENABLE                            (1 << 19)
+
 #define MC_SHARED_CHMAP                                                0x2004
 #define                NOOFCHAN_SHIFT                                  12
 #define                NOOFCHAN_MASK                                   0x0000f000
 
 #define MC_SHARED_BLACKOUT_CNTL                        0x20ac
 
+#define MC_HUB_MISC_HUB_CG                             0x20b8
+#define MC_HUB_MISC_VM_CG                              0x20bc
+
+#define MC_HUB_MISC_SIP_CG                             0x20c0
+
+#define MC_XPB_CLK_GAT                                 0x2478
+
+#define MC_CITF_MISC_RD_CG                             0x2648
+#define MC_CITF_MISC_WR_CG                             0x264c
+#define MC_CITF_MISC_VM_CG                             0x2650
+
 #define        MC_ARB_RAMCFG                                   0x2760
 #define                NOOFBANK_SHIFT                                  0
 #define                NOOFBANK_MASK                                   0x00000003
 #define MC_SEQ_IO_DEBUG_DATA                                   0x2a48
 
 #define        HDP_HOST_PATH_CNTL                              0x2C00
+#define        CLOCK_GATING_DIS                        (1 << 23)
 #define        HDP_NONSURFACE_BASE                             0x2C04
 #define        HDP_NONSURFACE_INFO                             0x2C08
 #define        HDP_NONSURFACE_SIZE                             0x2C0C
 #define HDP_ADDR_CONFIG                                0x2F48
 #define HDP_MISC_CNTL                                  0x2F4C
 #define        HDP_FLUSH_INVALIDATE_CACHE                      (1 << 0)
+#define HDP_MEM_POWER_LS                               0x2F50
+#define        HDP_LS_ENABLE                           (1 << 0)
+
+#define ATC_MISC_CG                                    0x3350
 
 #define IH_RB_CNTL                                        0x3e00
 #       define IH_RB_ENABLE                               (1 << 0)
 
 #define        CP_RB0_RPTR                                     0x8700
 #define        CP_RB_WPTR_DELAY                                0x8704
+#define        CP_RB_WPTR_POLL_CNTL                            0x8708
+#define                IDLE_POLL_COUNT(x)                      ((x) << 16)
+#define                IDLE_POLL_COUNT_MASK                    (0xffff << 16)
 
 #define CP_MEQ_THRESHOLDS                              0x8764
 #define                MEQ1_START(x)                           ((x) << 0)
 #       define CP_RINGID1_INT_STAT                      (1 << 30)
 #       define CP_RINGID0_INT_STAT                      (1 << 31)
 
+#define CP_MEM_SLP_CNTL                                 0xC1E4
+#       define CP_MEM_LS_EN                             (1 << 0)
+
 #define CP_CPF_DEBUG                                    0xC200
 
 #define CP_PQ_WPTR_POLL_CNTL                            0xC20C
 
 #define RLC_MC_CNTL                                       0xC30C
 
+#define RLC_MEM_SLP_CNTL                                  0xC318
+#       define RLC_MEM_LS_EN                              (1 << 0)
+
 #define RLC_LB_CNTR_MAX                                   0xC348
 
 #define RLC_LB_CNTL                                       0xC364
 #define RLC_LB_CNTR_INIT                                  0xC36C
 
 #define RLC_SAVE_AND_RESTORE_BASE                         0xC374
-#define RLC_DRIVER_DMA_STATUS                             0xC378
+#define RLC_DRIVER_DMA_STATUS                             0xC378 /* dGPU */
+#define RLC_CP_TABLE_RESTORE                              0xC378 /* APU */
+#define RLC_PG_DELAY_2                                    0xC37C
 
 #define RLC_GPM_UCODE_ADDR                                0xC388
 #define RLC_GPM_UCODE_DATA                                0xC38C
 #define RLC_CAPTURE_GPU_CLOCK_COUNT                       0xC398
 #define RLC_UCODE_CNTL                                    0xC39C
 
+#define RLC_GPM_STAT                                      0xC400
+#       define RLC_GPM_BUSY                               (1 << 0)
+
+#define RLC_PG_CNTL                                       0xC40C
+#       define GFX_PG_ENABLE                              (1 << 0)
+#       define GFX_PG_SRC                                 (1 << 1)
+#       define DYN_PER_CU_PG_ENABLE                       (1 << 2)
+#       define STATIC_PER_CU_PG_ENABLE                    (1 << 3)
+#       define DISABLE_GDS_PG                             (1 << 13)
+#       define DISABLE_CP_PG                              (1 << 15)
+#       define SMU_CLK_SLOWDOWN_ON_PU_ENABLE              (1 << 17)
+#       define SMU_CLK_SLOWDOWN_ON_PD_ENABLE              (1 << 18)
+
+#define RLC_CGTT_MGCG_OVERRIDE                            0xC420
 #define RLC_CGCG_CGLS_CTRL                                0xC424
+#       define CGCG_EN                                    (1 << 0)
+#       define CGLS_EN                                    (1 << 1)
+
+#define RLC_PG_DELAY                                      0xC434
 
 #define RLC_LB_INIT_CU_MASK                               0xC43C
 
 #define RLC_LB_PARAMS                                     0xC444
 
+#define RLC_PG_AO_CU_MASK                                 0xC44C
+
+#define        RLC_MAX_PG_CU                                   0xC450
+#      define MAX_PU_CU(x)                             ((x) << 0)
+#      define MAX_PU_CU_MASK                           (0xff << 0)
+#define RLC_AUTO_PG_CTRL                                  0xC454
+#       define AUTO_PG_EN                                 (1 << 0)
+#      define GRBM_REG_SGIT(x)                         ((x) << 3)
+#      define GRBM_REG_SGIT_MASK                       (0xffff << 3)
+
+#define RLC_SERDES_WR_CU_MASTER_MASK                      0xC474
+#define RLC_SERDES_WR_NONCU_MASTER_MASK                   0xC478
+#define RLC_SERDES_WR_CTRL                                0xC47C
+#define                BPM_ADDR(x)                             ((x) << 0)
+#define                BPM_ADDR_MASK                           (0xff << 0)
+#define                CGLS_ENABLE                             (1 << 16)
+#define                CGCG_OVERRIDE_0                         (1 << 20)
+#define                MGCG_OVERRIDE_0                         (1 << 22)
+#define                MGCG_OVERRIDE_1                         (1 << 23)
+
 #define RLC_SERDES_CU_MASTER_BUSY                         0xC484
 #define RLC_SERDES_NONCU_MASTER_BUSY                      0xC488
 #       define SE_MASTER_BUSY_MASK                        0x0000ffff
 #define                MQD_VMID(x)                             ((x) << 0)
 #define                MQD_VMID_MASK                           (0xf << 0)
 
+#define DB_RENDER_CONTROL                               0x28000
+
 #define PA_SC_RASTER_CONFIG                             0x28350
 #       define RASTER_CONFIG_RB_MAP_0                   0
 #       define RASTER_CONFIG_RB_MAP_1                   1
 
 #define        CP_PERFMON_CNTL                                 0x36020
 
+#define        CGTS_SM_CTRL_REG                                0x3c000
+#define                SM_MODE(x)                              ((x) << 17)
+#define                SM_MODE_MASK                            (0x7 << 17)
+#define                SM_MODE_ENABLE                          (1 << 20)
+#define                CGTS_OVERRIDE                           (1 << 21)
+#define                CGTS_LS_OVERRIDE                        (1 << 22)
+#define                ON_MONITOR_ADD_EN                       (1 << 23)
+#define                ON_MONITOR_ADD(x)                       ((x) << 24)
+#define                ON_MONITOR_ADD_MASK                     (0xff << 24)
+
 #define        CGTS_TCC_DISABLE                                0x3c00c
 #define        CGTS_USER_TCC_DISABLE                           0x3c010
 #define                TCC_DISABLE_MASK                                0xFFFF0000
 
 #define        SDMA0_UCODE_ADDR                                  0xD000
 #define        SDMA0_UCODE_DATA                                  0xD004
+#define        SDMA0_POWER_CNTL                                  0xD008
+#define        SDMA0_CLK_CTRL                                    0xD00C
 
 #define SDMA0_CNTL                                        0xD010
 #       define TRAP_ENABLE                                (1 << 0)
 #define UVD_RBC_RB_RPTR                        0xf690
 #define UVD_RBC_RB_WPTR                        0xf694
 
+#define        UVD_CGC_CTRL                                    0xF4B0
+#      define DCM                                      (1 << 0)
+#      define CG_DT(x)                                 ((x) << 2)
+#      define CG_DT_MASK                               (0xf << 2)
+#      define CLK_OD(x)                                ((x) << 6)
+#      define CLK_OD_MASK                              (0x1f << 6)
+
 /* UVD clocks */
 
 #define CG_DCLK_CNTL                   0xC050009C
 #define CG_VCLK_CNTL                   0xC05000A4
 #define CG_VCLK_STATUS                 0xC05000A8
 
+/* UVD CTX indirect */
+#define        UVD_CGC_MEM_CTRL                                0xC0
+
 #endif
diff --git a/drivers/gpu/drm/radeon/clearstate_ci.h b/drivers/gpu/drm/radeon/clearstate_ci.h
new file mode 100644 (file)
index 0000000..c3982f9
--- /dev/null
@@ -0,0 +1,944 @@
+/*
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+static const unsigned int ci_SECT_CONTEXT_def_1[] =
+{
+    0x00000000, // DB_RENDER_CONTROL
+    0x00000000, // DB_COUNT_CONTROL
+    0x00000000, // DB_DEPTH_VIEW
+    0x00000000, // DB_RENDER_OVERRIDE
+    0x00000000, // DB_RENDER_OVERRIDE2
+    0x00000000, // DB_HTILE_DATA_BASE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // DB_DEPTH_BOUNDS_MIN
+    0x00000000, // DB_DEPTH_BOUNDS_MAX
+    0x00000000, // DB_STENCIL_CLEAR
+    0x00000000, // DB_DEPTH_CLEAR
+    0x00000000, // PA_SC_SCREEN_SCISSOR_TL
+    0x40004000, // PA_SC_SCREEN_SCISSOR_BR
+    0, // HOLE
+    0x00000000, // DB_DEPTH_INFO
+    0x00000000, // DB_Z_INFO
+    0x00000000, // DB_STENCIL_INFO
+    0x00000000, // DB_Z_READ_BASE
+    0x00000000, // DB_STENCIL_READ_BASE
+    0x00000000, // DB_Z_WRITE_BASE
+    0x00000000, // DB_STENCIL_WRITE_BASE
+    0x00000000, // DB_DEPTH_SIZE
+    0x00000000, // DB_DEPTH_SLICE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // TA_BC_BASE_ADDR
+    0x00000000, // TA_BC_BASE_ADDR_HI
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // COHER_DEST_BASE_HI_0
+    0x00000000, // COHER_DEST_BASE_HI_1
+    0x00000000, // COHER_DEST_BASE_HI_2
+    0x00000000, // COHER_DEST_BASE_HI_3
+    0x00000000, // COHER_DEST_BASE_2
+    0x00000000, // COHER_DEST_BASE_3
+    0x00000000, // PA_SC_WINDOW_OFFSET
+    0x80000000, // PA_SC_WINDOW_SCISSOR_TL
+    0x40004000, // PA_SC_WINDOW_SCISSOR_BR
+    0x0000ffff, // PA_SC_CLIPRECT_RULE
+    0x00000000, // PA_SC_CLIPRECT_0_TL
+    0x40004000, // PA_SC_CLIPRECT_0_BR
+    0x00000000, // PA_SC_CLIPRECT_1_TL
+    0x40004000, // PA_SC_CLIPRECT_1_BR
+    0x00000000, // PA_SC_CLIPRECT_2_TL
+    0x40004000, // PA_SC_CLIPRECT_2_BR
+    0x00000000, // PA_SC_CLIPRECT_3_TL
+    0x40004000, // PA_SC_CLIPRECT_3_BR
+    0xaa99aaaa, // PA_SC_EDGERULE
+    0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET
+    0xffffffff, // CB_TARGET_MASK
+    0xffffffff, // CB_SHADER_MASK
+    0x80000000, // PA_SC_GENERIC_SCISSOR_TL
+    0x40004000, // PA_SC_GENERIC_SCISSOR_BR
+    0x00000000, // COHER_DEST_BASE_0
+    0x00000000, // COHER_DEST_BASE_1
+    0x80000000, // PA_SC_VPORT_SCISSOR_0_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_0_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_1_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_1_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_2_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_2_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_3_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_3_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_4_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_4_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_5_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_5_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_6_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_6_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_7_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_7_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_8_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_8_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_9_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_9_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_10_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_10_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_11_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_11_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_12_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_12_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_13_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_13_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_14_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_14_BR
+    0x80000000, // PA_SC_VPORT_SCISSOR_15_TL
+    0x40004000, // PA_SC_VPORT_SCISSOR_15_BR
+    0x00000000, // PA_SC_VPORT_ZMIN_0
+    0x3f800000, // PA_SC_VPORT_ZMAX_0
+    0x00000000, // PA_SC_VPORT_ZMIN_1
+    0x3f800000, // PA_SC_VPORT_ZMAX_1
+    0x00000000, // PA_SC_VPORT_ZMIN_2
+    0x3f800000, // PA_SC_VPORT_ZMAX_2
+    0x00000000, // PA_SC_VPORT_ZMIN_3
+    0x3f800000, // PA_SC_VPORT_ZMAX_3
+    0x00000000, // PA_SC_VPORT_ZMIN_4
+    0x3f800000, // PA_SC_VPORT_ZMAX_4
+    0x00000000, // PA_SC_VPORT_ZMIN_5
+    0x3f800000, // PA_SC_VPORT_ZMAX_5
+    0x00000000, // PA_SC_VPORT_ZMIN_6
+    0x3f800000, // PA_SC_VPORT_ZMAX_6
+    0x00000000, // PA_SC_VPORT_ZMIN_7
+    0x3f800000, // PA_SC_VPORT_ZMAX_7
+    0x00000000, // PA_SC_VPORT_ZMIN_8
+    0x3f800000, // PA_SC_VPORT_ZMAX_8
+    0x00000000, // PA_SC_VPORT_ZMIN_9
+    0x3f800000, // PA_SC_VPORT_ZMAX_9
+    0x00000000, // PA_SC_VPORT_ZMIN_10
+    0x3f800000, // PA_SC_VPORT_ZMAX_10
+    0x00000000, // PA_SC_VPORT_ZMIN_11
+    0x3f800000, // PA_SC_VPORT_ZMAX_11
+    0x00000000, // PA_SC_VPORT_ZMIN_12
+    0x3f800000, // PA_SC_VPORT_ZMAX_12
+    0x00000000, // PA_SC_VPORT_ZMIN_13
+    0x3f800000, // PA_SC_VPORT_ZMAX_13
+    0x00000000, // PA_SC_VPORT_ZMIN_14
+    0x3f800000, // PA_SC_VPORT_ZMAX_14
+    0x00000000, // PA_SC_VPORT_ZMIN_15
+    0x3f800000, // PA_SC_VPORT_ZMAX_15
+};
+static const unsigned int ci_SECT_CONTEXT_def_2[] =
+{
+    0x00000000, // PA_SC_SCREEN_EXTENT_CONTROL
+    0, // HOLE
+    0x00000000, // CP_PERFMON_CNTX_CNTL
+    0x00000000, // CP_RINGID
+    0x00000000, // CP_VMID
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0xffffffff, // VGT_MAX_VTX_INDX
+    0x00000000, // VGT_MIN_VTX_INDX
+    0x00000000, // VGT_INDX_OFFSET
+    0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX
+    0, // HOLE
+    0x00000000, // CB_BLEND_RED
+    0x00000000, // CB_BLEND_GREEN
+    0x00000000, // CB_BLEND_BLUE
+    0x00000000, // CB_BLEND_ALPHA
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // DB_STENCIL_CONTROL
+    0x00000000, // DB_STENCILREFMASK
+    0x00000000, // DB_STENCILREFMASK_BF
+    0, // HOLE
+    0x00000000, // PA_CL_VPORT_XSCALE
+    0x00000000, // PA_CL_VPORT_XOFFSET
+    0x00000000, // PA_CL_VPORT_YSCALE
+    0x00000000, // PA_CL_VPORT_YOFFSET
+    0x00000000, // PA_CL_VPORT_ZSCALE
+    0x00000000, // PA_CL_VPORT_ZOFFSET
+    0x00000000, // PA_CL_VPORT_XSCALE_1
+    0x00000000, // PA_CL_VPORT_XOFFSET_1
+    0x00000000, // PA_CL_VPORT_YSCALE_1
+    0x00000000, // PA_CL_VPORT_YOFFSET_1
+    0x00000000, // PA_CL_VPORT_ZSCALE_1
+    0x00000000, // PA_CL_VPORT_ZOFFSET_1
+    0x00000000, // PA_CL_VPORT_XSCALE_2
+    0x00000000, // PA_CL_VPORT_XOFFSET_2
+    0x00000000, // PA_CL_VPORT_YSCALE_2
+    0x00000000, // PA_CL_VPORT_YOFFSET_2
+    0x00000000, // PA_CL_VPORT_ZSCALE_2
+    0x00000000, // PA_CL_VPORT_ZOFFSET_2
+    0x00000000, // PA_CL_VPORT_XSCALE_3
+    0x00000000, // PA_CL_VPORT_XOFFSET_3
+    0x00000000, // PA_CL_VPORT_YSCALE_3
+    0x00000000, // PA_CL_VPORT_YOFFSET_3
+    0x00000000, // PA_CL_VPORT_ZSCALE_3
+    0x00000000, // PA_CL_VPORT_ZOFFSET_3
+    0x00000000, // PA_CL_VPORT_XSCALE_4
+    0x00000000, // PA_CL_VPORT_XOFFSET_4
+    0x00000000, // PA_CL_VPORT_YSCALE_4
+    0x00000000, // PA_CL_VPORT_YOFFSET_4
+    0x00000000, // PA_CL_VPORT_ZSCALE_4
+    0x00000000, // PA_CL_VPORT_ZOFFSET_4
+    0x00000000, // PA_CL_VPORT_XSCALE_5
+    0x00000000, // PA_CL_VPORT_XOFFSET_5
+    0x00000000, // PA_CL_VPORT_YSCALE_5
+    0x00000000, // PA_CL_VPORT_YOFFSET_5
+    0x00000000, // PA_CL_VPORT_ZSCALE_5
+    0x00000000, // PA_CL_VPORT_ZOFFSET_5
+    0x00000000, // PA_CL_VPORT_XSCALE_6
+    0x00000000, // PA_CL_VPORT_XOFFSET_6
+    0x00000000, // PA_CL_VPORT_YSCALE_6
+    0x00000000, // PA_CL_VPORT_YOFFSET_6
+    0x00000000, // PA_CL_VPORT_ZSCALE_6
+    0x00000000, // PA_CL_VPORT_ZOFFSET_6
+    0x00000000, // PA_CL_VPORT_XSCALE_7
+    0x00000000, // PA_CL_VPORT_XOFFSET_7
+    0x00000000, // PA_CL_VPORT_YSCALE_7
+    0x00000000, // PA_CL_VPORT_YOFFSET_7
+    0x00000000, // PA_CL_VPORT_ZSCALE_7
+    0x00000000, // PA_CL_VPORT_ZOFFSET_7
+    0x00000000, // PA_CL_VPORT_XSCALE_8
+    0x00000000, // PA_CL_VPORT_XOFFSET_8
+    0x00000000, // PA_CL_VPORT_YSCALE_8
+    0x00000000, // PA_CL_VPORT_YOFFSET_8
+    0x00000000, // PA_CL_VPORT_ZSCALE_8
+    0x00000000, // PA_CL_VPORT_ZOFFSET_8
+    0x00000000, // PA_CL_VPORT_XSCALE_9
+    0x00000000, // PA_CL_VPORT_XOFFSET_9
+    0x00000000, // PA_CL_VPORT_YSCALE_9
+    0x00000000, // PA_CL_VPORT_YOFFSET_9
+    0x00000000, // PA_CL_VPORT_ZSCALE_9
+    0x00000000, // PA_CL_VPORT_ZOFFSET_9
+    0x00000000, // PA_CL_VPORT_XSCALE_10
+    0x00000000, // PA_CL_VPORT_XOFFSET_10
+    0x00000000, // PA_CL_VPORT_YSCALE_10
+    0x00000000, // PA_CL_VPORT_YOFFSET_10
+    0x00000000, // PA_CL_VPORT_ZSCALE_10
+    0x00000000, // PA_CL_VPORT_ZOFFSET_10
+    0x00000000, // PA_CL_VPORT_XSCALE_11
+    0x00000000, // PA_CL_VPORT_XOFFSET_11
+    0x00000000, // PA_CL_VPORT_YSCALE_11
+    0x00000000, // PA_CL_VPORT_YOFFSET_11
+    0x00000000, // PA_CL_VPORT_ZSCALE_11
+    0x00000000, // PA_CL_VPORT_ZOFFSET_11
+    0x00000000, // PA_CL_VPORT_XSCALE_12
+    0x00000000, // PA_CL_VPORT_XOFFSET_12
+    0x00000000, // PA_CL_VPORT_YSCALE_12
+    0x00000000, // PA_CL_VPORT_YOFFSET_12
+    0x00000000, // PA_CL_VPORT_ZSCALE_12
+    0x00000000, // PA_CL_VPORT_ZOFFSET_12
+    0x00000000, // PA_CL_VPORT_XSCALE_13
+    0x00000000, // PA_CL_VPORT_XOFFSET_13
+    0x00000000, // PA_CL_VPORT_YSCALE_13
+    0x00000000, // PA_CL_VPORT_YOFFSET_13
+    0x00000000, // PA_CL_VPORT_ZSCALE_13
+    0x00000000, // PA_CL_VPORT_ZOFFSET_13
+    0x00000000, // PA_CL_VPORT_XSCALE_14
+    0x00000000, // PA_CL_VPORT_XOFFSET_14
+    0x00000000, // PA_CL_VPORT_YSCALE_14
+    0x00000000, // PA_CL_VPORT_YOFFSET_14
+    0x00000000, // PA_CL_VPORT_ZSCALE_14
+    0x00000000, // PA_CL_VPORT_ZOFFSET_14
+    0x00000000, // PA_CL_VPORT_XSCALE_15
+    0x00000000, // PA_CL_VPORT_XOFFSET_15
+    0x00000000, // PA_CL_VPORT_YSCALE_15
+    0x00000000, // PA_CL_VPORT_YOFFSET_15
+    0x00000000, // PA_CL_VPORT_ZSCALE_15
+    0x00000000, // PA_CL_VPORT_ZOFFSET_15
+    0x00000000, // PA_CL_UCP_0_X
+    0x00000000, // PA_CL_UCP_0_Y
+    0x00000000, // PA_CL_UCP_0_Z
+    0x00000000, // PA_CL_UCP_0_W
+    0x00000000, // PA_CL_UCP_1_X
+    0x00000000, // PA_CL_UCP_1_Y
+    0x00000000, // PA_CL_UCP_1_Z
+    0x00000000, // PA_CL_UCP_1_W
+    0x00000000, // PA_CL_UCP_2_X
+    0x00000000, // PA_CL_UCP_2_Y
+    0x00000000, // PA_CL_UCP_2_Z
+    0x00000000, // PA_CL_UCP_2_W
+    0x00000000, // PA_CL_UCP_3_X
+    0x00000000, // PA_CL_UCP_3_Y
+    0x00000000, // PA_CL_UCP_3_Z
+    0x00000000, // PA_CL_UCP_3_W
+    0x00000000, // PA_CL_UCP_4_X
+    0x00000000, // PA_CL_UCP_4_Y
+    0x00000000, // PA_CL_UCP_4_Z
+    0x00000000, // PA_CL_UCP_4_W
+    0x00000000, // PA_CL_UCP_5_X
+    0x00000000, // PA_CL_UCP_5_Y
+    0x00000000, // PA_CL_UCP_5_Z
+    0x00000000, // PA_CL_UCP_5_W
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // SPI_PS_INPUT_CNTL_0
+    0x00000000, // SPI_PS_INPUT_CNTL_1
+    0x00000000, // SPI_PS_INPUT_CNTL_2
+    0x00000000, // SPI_PS_INPUT_CNTL_3
+    0x00000000, // SPI_PS_INPUT_CNTL_4
+    0x00000000, // SPI_PS_INPUT_CNTL_5
+    0x00000000, // SPI_PS_INPUT_CNTL_6
+    0x00000000, // SPI_PS_INPUT_CNTL_7
+    0x00000000, // SPI_PS_INPUT_CNTL_8
+    0x00000000, // SPI_PS_INPUT_CNTL_9
+    0x00000000, // SPI_PS_INPUT_CNTL_10
+    0x00000000, // SPI_PS_INPUT_CNTL_11
+    0x00000000, // SPI_PS_INPUT_CNTL_12
+    0x00000000, // SPI_PS_INPUT_CNTL_13
+    0x00000000, // SPI_PS_INPUT_CNTL_14
+    0x00000000, // SPI_PS_INPUT_CNTL_15
+    0x00000000, // SPI_PS_INPUT_CNTL_16
+    0x00000000, // SPI_PS_INPUT_CNTL_17
+    0x00000000, // SPI_PS_INPUT_CNTL_18
+    0x00000000, // SPI_PS_INPUT_CNTL_19
+    0x00000000, // SPI_PS_INPUT_CNTL_20
+    0x00000000, // SPI_PS_INPUT_CNTL_21
+    0x00000000, // SPI_PS_INPUT_CNTL_22
+    0x00000000, // SPI_PS_INPUT_CNTL_23
+    0x00000000, // SPI_PS_INPUT_CNTL_24
+    0x00000000, // SPI_PS_INPUT_CNTL_25
+    0x00000000, // SPI_PS_INPUT_CNTL_26
+    0x00000000, // SPI_PS_INPUT_CNTL_27
+    0x00000000, // SPI_PS_INPUT_CNTL_28
+    0x00000000, // SPI_PS_INPUT_CNTL_29
+    0x00000000, // SPI_PS_INPUT_CNTL_30
+    0x00000000, // SPI_PS_INPUT_CNTL_31
+    0x00000000, // SPI_VS_OUT_CONFIG
+    0, // HOLE
+    0x00000000, // SPI_PS_INPUT_ENA
+    0x00000000, // SPI_PS_INPUT_ADDR
+    0x00000000, // SPI_INTERP_CONTROL_0
+    0x00000002, // SPI_PS_IN_CONTROL
+    0, // HOLE
+    0x00000000, // SPI_BARYC_CNTL
+    0, // HOLE
+    0x00000000, // SPI_TMPRING_SIZE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // SPI_SHADER_POS_FORMAT
+    0x00000000, // SPI_SHADER_Z_FORMAT
+    0x00000000, // SPI_SHADER_COL_FORMAT
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_BLEND0_CONTROL
+    0x00000000, // CB_BLEND1_CONTROL
+    0x00000000, // CB_BLEND2_CONTROL
+    0x00000000, // CB_BLEND3_CONTROL
+    0x00000000, // CB_BLEND4_CONTROL
+    0x00000000, // CB_BLEND5_CONTROL
+    0x00000000, // CB_BLEND6_CONTROL
+    0x00000000, // CB_BLEND7_CONTROL
+};
+static const unsigned int ci_SECT_CONTEXT_def_3[] =
+{
+    0x00000000, // PA_CL_POINT_X_RAD
+    0x00000000, // PA_CL_POINT_Y_RAD
+    0x00000000, // PA_CL_POINT_SIZE
+    0x00000000, // PA_CL_POINT_CULL_RAD
+    0x00000000, // VGT_DMA_BASE_HI
+    0x00000000, // VGT_DMA_BASE
+};
+static const unsigned int ci_SECT_CONTEXT_def_4[] =
+{
+    0x00000000, // DB_DEPTH_CONTROL
+    0x00000000, // DB_EQAA
+    0x00000000, // CB_COLOR_CONTROL
+    0x00000000, // DB_SHADER_CONTROL
+    0x00090000, // PA_CL_CLIP_CNTL
+    0x00000004, // PA_SU_SC_MODE_CNTL
+    0x00000000, // PA_CL_VTE_CNTL
+    0x00000000, // PA_CL_VS_OUT_CNTL
+    0x00000000, // PA_CL_NANINF_CNTL
+    0x00000000, // PA_SU_LINE_STIPPLE_CNTL
+    0x00000000, // PA_SU_LINE_STIPPLE_SCALE
+    0x00000000, // PA_SU_PRIM_FILTER_CNTL
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // PA_SU_POINT_SIZE
+    0x00000000, // PA_SU_POINT_MINMAX
+    0x00000000, // PA_SU_LINE_CNTL
+    0x00000000, // PA_SC_LINE_STIPPLE
+    0x00000000, // VGT_OUTPUT_PATH_CNTL
+    0x00000000, // VGT_HOS_CNTL
+    0x00000000, // VGT_HOS_MAX_TESS_LEVEL
+    0x00000000, // VGT_HOS_MIN_TESS_LEVEL
+    0x00000000, // VGT_HOS_REUSE_DEPTH
+    0x00000000, // VGT_GROUP_PRIM_TYPE
+    0x00000000, // VGT_GROUP_FIRST_DECR
+    0x00000000, // VGT_GROUP_DECR
+    0x00000000, // VGT_GROUP_VECT_0_CNTL
+    0x00000000, // VGT_GROUP_VECT_1_CNTL
+    0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL
+    0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL
+    0x00000000, // VGT_GS_MODE
+    0x00000000, // VGT_GS_ONCHIP_CNTL
+    0x00000000, // PA_SC_MODE_CNTL_0
+    0x00000000, // PA_SC_MODE_CNTL_1
+    0x00000000, // VGT_ENHANCE
+    0x00000100, // VGT_GS_PER_ES
+    0x00000080, // VGT_ES_PER_GS
+    0x00000002, // VGT_GS_PER_VS
+    0x00000000, // VGT_GSVS_RING_OFFSET_1
+    0x00000000, // VGT_GSVS_RING_OFFSET_2
+    0x00000000, // VGT_GSVS_RING_OFFSET_3
+    0x00000000, // VGT_GS_OUT_PRIM_TYPE
+    0x00000000, // IA_ENHANCE
+};
+static const unsigned int ci_SECT_CONTEXT_def_5[] =
+{
+    0x00000000, // WD_ENHANCE
+    0x00000000, // VGT_PRIMITIVEID_EN
+};
+static const unsigned int ci_SECT_CONTEXT_def_6[] =
+{
+    0x00000000, // VGT_PRIMITIVEID_RESET
+};
+static const unsigned int ci_SECT_CONTEXT_def_7[] =
+{
+    0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // VGT_INSTANCE_STEP_RATE_0
+    0x00000000, // VGT_INSTANCE_STEP_RATE_1
+    0x000000ff, // IA_MULTI_VGT_PARAM
+    0x00000000, // VGT_ESGS_RING_ITEMSIZE
+    0x00000000, // VGT_GSVS_RING_ITEMSIZE
+    0x00000000, // VGT_REUSE_OFF
+    0x00000000, // VGT_VTX_CNT_EN
+    0x00000000, // DB_HTILE_SURFACE
+    0x00000000, // DB_SRESULTS_COMPARE_STATE0
+    0x00000000, // DB_SRESULTS_COMPARE_STATE1
+    0x00000000, // DB_PRELOAD_CONTROL
+    0, // HOLE
+    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0
+    0x00000000, // VGT_STRMOUT_VTX_STRIDE_0
+    0, // HOLE
+    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0
+    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1
+    0x00000000, // VGT_STRMOUT_VTX_STRIDE_1
+    0, // HOLE
+    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1
+    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2
+    0x00000000, // VGT_STRMOUT_VTX_STRIDE_2
+    0, // HOLE
+    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2
+    0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3
+    0x00000000, // VGT_STRMOUT_VTX_STRIDE_3
+    0, // HOLE
+    0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET
+    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
+    0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
+    0, // HOLE
+    0x00000000, // VGT_GS_MAX_VERT_OUT
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // VGT_SHADER_STAGES_EN
+    0x00000000, // VGT_LS_HS_CONFIG
+    0x00000000, // VGT_GS_VERT_ITEMSIZE
+    0x00000000, // VGT_GS_VERT_ITEMSIZE_1
+    0x00000000, // VGT_GS_VERT_ITEMSIZE_2
+    0x00000000, // VGT_GS_VERT_ITEMSIZE_3
+    0x00000000, // VGT_TF_PARAM
+    0x00000000, // DB_ALPHA_TO_MASK
+    0, // HOLE
+    0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL
+    0x00000000, // PA_SU_POLY_OFFSET_CLAMP
+    0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE
+    0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET
+    0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE
+    0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET
+    0x00000000, // VGT_GS_INSTANCE_CNT
+    0x00000000, // VGT_STRMOUT_CONFIG
+    0x00000000, // VGT_STRMOUT_BUFFER_CONFIG
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // PA_SC_CENTROID_PRIORITY_0
+    0x00000000, // PA_SC_CENTROID_PRIORITY_1
+    0x00001000, // PA_SC_LINE_CNTL
+    0x00000000, // PA_SC_AA_CONFIG
+    0x00000005, // PA_SU_VTX_CNTL
+    0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ
+    0x3f800000, // PA_CL_GB_VERT_DISC_ADJ
+    0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ
+    0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
+    0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
+    0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0
+    0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0, // HOLE
+    0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL
+    0x00000010, // VGT_OUT_DEALLOC_CNTL
+    0x00000000, // CB_COLOR0_BASE
+    0x00000000, // CB_COLOR0_PITCH
+    0x00000000, // CB_COLOR0_SLICE
+    0x00000000, // CB_COLOR0_VIEW
+    0x00000000, // CB_COLOR0_INFO
+    0x00000000, // CB_COLOR0_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR0_CMASK
+    0x00000000, // CB_COLOR0_CMASK_SLICE
+    0x00000000, // CB_COLOR0_FMASK
+    0x00000000, // CB_COLOR0_FMASK_SLICE
+    0x00000000, // CB_COLOR0_CLEAR_WORD0
+    0x00000000, // CB_COLOR0_CLEAR_WORD1
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_COLOR1_BASE
+    0x00000000, // CB_COLOR1_PITCH
+    0x00000000, // CB_COLOR1_SLICE
+    0x00000000, // CB_COLOR1_VIEW
+    0x00000000, // CB_COLOR1_INFO
+    0x00000000, // CB_COLOR1_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR1_CMASK
+    0x00000000, // CB_COLOR1_CMASK_SLICE
+    0x00000000, // CB_COLOR1_FMASK
+    0x00000000, // CB_COLOR1_FMASK_SLICE
+    0x00000000, // CB_COLOR1_CLEAR_WORD0
+    0x00000000, // CB_COLOR1_CLEAR_WORD1
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_COLOR2_BASE
+    0x00000000, // CB_COLOR2_PITCH
+    0x00000000, // CB_COLOR2_SLICE
+    0x00000000, // CB_COLOR2_VIEW
+    0x00000000, // CB_COLOR2_INFO
+    0x00000000, // CB_COLOR2_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR2_CMASK
+    0x00000000, // CB_COLOR2_CMASK_SLICE
+    0x00000000, // CB_COLOR2_FMASK
+    0x00000000, // CB_COLOR2_FMASK_SLICE
+    0x00000000, // CB_COLOR2_CLEAR_WORD0
+    0x00000000, // CB_COLOR2_CLEAR_WORD1
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_COLOR3_BASE
+    0x00000000, // CB_COLOR3_PITCH
+    0x00000000, // CB_COLOR3_SLICE
+    0x00000000, // CB_COLOR3_VIEW
+    0x00000000, // CB_COLOR3_INFO
+    0x00000000, // CB_COLOR3_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR3_CMASK
+    0x00000000, // CB_COLOR3_CMASK_SLICE
+    0x00000000, // CB_COLOR3_FMASK
+    0x00000000, // CB_COLOR3_FMASK_SLICE
+    0x00000000, // CB_COLOR3_CLEAR_WORD0
+    0x00000000, // CB_COLOR3_CLEAR_WORD1
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_COLOR4_BASE
+    0x00000000, // CB_COLOR4_PITCH
+    0x00000000, // CB_COLOR4_SLICE
+    0x00000000, // CB_COLOR4_VIEW
+    0x00000000, // CB_COLOR4_INFO
+    0x00000000, // CB_COLOR4_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR4_CMASK
+    0x00000000, // CB_COLOR4_CMASK_SLICE
+    0x00000000, // CB_COLOR4_FMASK
+    0x00000000, // CB_COLOR4_FMASK_SLICE
+    0x00000000, // CB_COLOR4_CLEAR_WORD0
+    0x00000000, // CB_COLOR4_CLEAR_WORD1
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_COLOR5_BASE
+    0x00000000, // CB_COLOR5_PITCH
+    0x00000000, // CB_COLOR5_SLICE
+    0x00000000, // CB_COLOR5_VIEW
+    0x00000000, // CB_COLOR5_INFO
+    0x00000000, // CB_COLOR5_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR5_CMASK
+    0x00000000, // CB_COLOR5_CMASK_SLICE
+    0x00000000, // CB_COLOR5_FMASK
+    0x00000000, // CB_COLOR5_FMASK_SLICE
+    0x00000000, // CB_COLOR5_CLEAR_WORD0
+    0x00000000, // CB_COLOR5_CLEAR_WORD1
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_COLOR6_BASE
+    0x00000000, // CB_COLOR6_PITCH
+    0x00000000, // CB_COLOR6_SLICE
+    0x00000000, // CB_COLOR6_VIEW
+    0x00000000, // CB_COLOR6_INFO
+    0x00000000, // CB_COLOR6_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR6_CMASK
+    0x00000000, // CB_COLOR6_CMASK_SLICE
+    0x00000000, // CB_COLOR6_FMASK
+    0x00000000, // CB_COLOR6_FMASK_SLICE
+    0x00000000, // CB_COLOR6_CLEAR_WORD0
+    0x00000000, // CB_COLOR6_CLEAR_WORD1
+    0, // HOLE
+    0, // HOLE
+    0x00000000, // CB_COLOR7_BASE
+    0x00000000, // CB_COLOR7_PITCH
+    0x00000000, // CB_COLOR7_SLICE
+    0x00000000, // CB_COLOR7_VIEW
+    0x00000000, // CB_COLOR7_INFO
+    0x00000000, // CB_COLOR7_ATTRIB
+    0, // HOLE
+    0x00000000, // CB_COLOR7_CMASK
+    0x00000000, // CB_COLOR7_CMASK_SLICE
+    0x00000000, // CB_COLOR7_FMASK
+    0x00000000, // CB_COLOR7_FMASK_SLICE
+    0x00000000, // CB_COLOR7_CLEAR_WORD0
+    0x00000000, // CB_COLOR7_CLEAR_WORD1
+};
+static const struct cs_extent_def ci_SECT_CONTEXT_defs[] =
+{
+    {ci_SECT_CONTEXT_def_1, 0x0000a000, 212 },
+    {ci_SECT_CONTEXT_def_2, 0x0000a0d6, 274 },
+    {ci_SECT_CONTEXT_def_3, 0x0000a1f5, 6 },
+    {ci_SECT_CONTEXT_def_4, 0x0000a200, 157 },
+    {ci_SECT_CONTEXT_def_5, 0x0000a2a0, 2 },
+    {ci_SECT_CONTEXT_def_6, 0x0000a2a3, 1 },
+    {ci_SECT_CONTEXT_def_7, 0x0000a2a5, 233 },
+    { 0, 0, 0 }
+};
+static const struct cs_section_def ci_cs_data[] = {
+    { ci_SECT_CONTEXT_defs, SECT_CONTEXT },
+    { 0, SECT_NONE }
+};
index 6fc876a444d476f7fd5e1c75a6bfa405783aebf5..2ce12ee3e67f4cc64eb9594a09408a63858b38be 100644 (file)
@@ -140,6 +140,7 @@ extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
                                     int ring, u32 cp_int_cntl);
 extern void cayman_vm_decode_fault(struct radeon_device *rdev,
                                   u32 status, u32 addr);
+void cik_init_cp_pg_table(struct radeon_device *rdev);
 
 static const u32 evergreen_golden_registers[] =
 {
@@ -3893,8 +3894,22 @@ void sumo_rlc_fini(struct radeon_device *rdev)
                radeon_bo_unref(&rdev->rlc.clear_state_obj);
                rdev->rlc.clear_state_obj = NULL;
        }
+
+       /* clear state block */
+       if (rdev->rlc.cp_table_obj) {
+               r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
+               if (unlikely(r != 0))
+                       dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
+               radeon_bo_unpin(rdev->rlc.cp_table_obj);
+               radeon_bo_unreserve(rdev->rlc.cp_table_obj);
+
+               radeon_bo_unref(&rdev->rlc.cp_table_obj);
+               rdev->rlc.cp_table_obj = NULL;
+       }
 }
 
+#define CP_ME_TABLE_SIZE    96
+
 int sumo_rlc_init(struct radeon_device *rdev)
 {
        const u32 *src_ptr;
@@ -3980,9 +3995,10 @@ int sumo_rlc_init(struct radeon_device *rdev)
                }
                reg_list_blk_index = (3 * reg_list_num + 2);
                dws += reg_list_blk_index;
+               rdev->rlc.clear_state_size = dws;
 
                if (rdev->rlc.clear_state_obj == NULL) {
-                       r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
+                       r = radeon_bo_create(rdev, rdev->rlc.clear_state_size * 4, PAGE_SIZE, true,
                                             RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
                        if (r) {
                                dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
@@ -4046,6 +4062,45 @@ int sumo_rlc_init(struct radeon_device *rdev)
                radeon_bo_unreserve(rdev->rlc.clear_state_obj);
        }
 
+       if (rdev->rlc.cp_table_size) {
+               if (rdev->rlc.cp_table_obj == NULL) {
+                       r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, PAGE_SIZE, true,
+                                            RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.cp_table_obj);
+                       if (r) {
+                               dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
+                               sumo_rlc_fini(rdev);
+                               return r;
+                       }
+               }
+
+               r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
+               if (unlikely(r != 0)) {
+                       dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
+                       sumo_rlc_fini(rdev);
+                       return r;
+               }
+               r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,
+                                 &rdev->rlc.cp_table_gpu_addr);
+               if (r) {
+                       radeon_bo_unreserve(rdev->rlc.cp_table_obj);
+                       dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r);
+                       sumo_rlc_fini(rdev);
+                       return r;
+               }
+               r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);
+               if (r) {
+                       dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r);
+                       sumo_rlc_fini(rdev);
+                       return r;
+               }
+
+               cik_init_cp_pg_table(rdev);
+
+               radeon_bo_kunmap(rdev->rlc.cp_table_obj);
+               radeon_bo_unreserve(rdev->rlc.cp_table_obj);
+
+       }
+
        return 0;
 }
 
index b9706e83e8270a332d9554c2bc314cf288ce4ed5..5941ada063d1fa16964204a0bfbc0dba3f8cebf0 100644 (file)
@@ -152,6 +152,14 @@ extern int radeon_aspm;
 #define RADEON_RESET_MC                                (1 << 10)
 #define RADEON_RESET_DISPLAY                   (1 << 11)
 
+/* CG block flags */
+#define RADEON_CG_BLOCK_GFX                    (1 << 0)
+#define RADEON_CG_BLOCK_MC                     (1 << 1)
+#define RADEON_CG_BLOCK_SDMA                   (1 << 2)
+#define RADEON_CG_BLOCK_UVD                    (1 << 3)
+#define RADEON_CG_BLOCK_VCE                    (1 << 4)
+#define RADEON_CG_BLOCK_HDP                    (1 << 5)
+
 /* max cursor sizes (in pixels) */
 #define CURSOR_WIDTH 64
 #define CURSOR_HEIGHT 64
@@ -861,6 +869,12 @@ struct radeon_rlc {
        uint64_t                clear_state_gpu_addr;
        volatile uint32_t       *cs_ptr;
        const struct cs_section_def   *cs_data;
+       u32                     clear_state_size;
+       /* for cp tables */
+       struct radeon_bo        *cp_table_obj;
+       uint64_t                cp_table_gpu_addr;
+       volatile uint32_t       *cp_table_ptr;
+       u32                     cp_table_size;
 };
 
 int radeon_ib_get(struct radeon_device *rdev, int ring,
index 1926ec06a6385c9c562fedcf0b00da7b9a1495d3..880551b6df619ff895a08b54c3da5591f698c9c1 100644 (file)
@@ -2780,6 +2780,7 @@ int radeon_asic_init(struct radeon_device *rdev)
        case CHIP_BONAIRE:
                rdev->asic = &ci_asic;
                rdev->num_crtc = 6;
+               rdev->has_uvd = true;
                break;
        case CHIP_KAVERI:
        case CHIP_KABINI:
@@ -2789,6 +2790,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                        rdev->num_crtc = 4;
                else
                        rdev->num_crtc = 2;
+               rdev->has_uvd = true;
                break;
        default:
                /* FIXME: not supported yet */
index 8b8963d4a732e2338fe1d42b14118e5b71b0293c..4f91e1f4d8147c7aee573ccf45de8efd02f47e74 100644 (file)
@@ -4901,7 +4901,7 @@ static void si_set_uvd_dcm(struct radeon_device *rdev,
        WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2);
 }
 
-static void si_init_uvd_internal_cg(struct radeon_device *rdev)
+void si_init_uvd_internal_cg(struct radeon_device *rdev)
 {
        bool hw_mode = true;