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[Hexagon] Fixing 224952 where an addressing mode update was missed.
author
Colin LeMahieu
<colinl@codeaurora.org>
Mon, 29 Dec 2014 21:18:02 +0000
(21:18 +0000)
committer
Colin LeMahieu
<colinl@codeaurora.org>
Mon, 29 Dec 2014 21:18:02 +0000
(21:18 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224955
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/Hexagon/HexagonInstrInfo.td
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diff --git
a/lib/Target/Hexagon/HexagonInstrInfo.td
b/lib/Target/Hexagon/HexagonInstrInfo.td
index f16cfe14322a6f0598b9297db230a974eb5ec765..565aed7062ab56ad1da13892227b6528ffd484b5 100644
(file)
--- a/
lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/
lib/Target/Hexagon/HexagonInstrInfo.td
@@
-4124,7
+4124,7
@@
def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
// Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
- (S2_storerb_io A
DDRriS11_2
:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
+ (S2_storerb_io A
ddrFI
:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
// Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
// Hexagon_TODO: We can probably use combine but that will cost 2 instructions.