Fix inverted preprocessor conditional.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76111 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index a859d80e1b732f6cc6dad3aa91c0cb3656e2395f..61ea80b3d9deeb7a81f2bb577c045f6f26842df9 100644 (file)
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -491,7 +491,7 @@ static void ReMaterialize(MachineBasicBlock &MBB,
                           const TargetRegisterInfo *TRI,
                           VirtRegMap &VRM) {
   MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
-#ifdef NDEBUG
+#ifndef NDEBUG
   const TargetInstrDesc &TID = ReMatDefMI->getDesc();
   assert(TID.getNumDefs() != 1 &&
          "Don't know how to remat instructions that define > 1 values!");