x86, VisWS: turn into generic arch, clean up
authorIngo Molnar <mingo@elte.hu>
Thu, 10 Jul 2008 14:21:38 +0000 (16:21 +0200)
committerIngo Molnar <mingo@elte.hu>
Thu, 10 Jul 2008 16:55:45 +0000 (18:55 +0200)
merge traps_visws.c and apic_visws.c into visws_quirks.c.

(no code changed)

Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/Makefile
arch/x86/kernel/apic_visws.c [deleted file]
arch/x86/kernel/traps_visws.c [deleted file]
arch/x86/kernel/visws_quirks.c

index 2ef0fbd3488f793760676205e87a18eccab08abb..f77dd6774bbae1b3d3284e7f054d32b2baa4378b 100644 (file)
@@ -19,7 +19,7 @@ obj-y                 := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o
 obj-y                  += traps_$(BITS).o irq_$(BITS).o
 obj-y                  += time_$(BITS).o ioport.o ldt.o
 obj-y                  += setup.o i8259.o irqinit_$(BITS).o setup_percpu.o
-obj-$(CONFIG_X86_VISWS)        += visws_quirks.o traps_visws.o apic_visws.o
+obj-$(CONFIG_X86_VISWS)        += visws_quirks.o
 obj-$(CONFIG_X86_32)   += probe_roms_32.o
 obj-$(CONFIG_X86_32)   += sys_i386_32.o i386_ksyms_32.o
 obj-$(CONFIG_X86_64)   += sys_x86_64.o x8664_ksyms_64.o
diff --git a/arch/x86/kernel/apic_visws.c b/arch/x86/kernel/apic_visws.c
deleted file mode 100644 (file)
index 6c02c8d..0000000
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- *     Copyright (C) 1999 Bent Hagemark, Ingo Molnar
- *
- *  SGI Visual Workstation interrupt controller
- *
- *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
- *  which serves as the main interrupt controller in the system.  Non-legacy
- *  hardware in the system uses this controller directly.  Legacy devices
- *  are connected to the PIIX4 which in turn has its 8259(s) connected to
- *  a of the Cobalt APIC entry.
- *
- *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
- *
- *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/io.h>
-#include <asm/apic.h>
-#include <asm/i8259.h>
-#include <asm/irq_vectors.h>
-#include <asm/visws/cobalt.h>
-
-static DEFINE_SPINLOCK(cobalt_lock);
-
-/*
- * Set the given Cobalt APIC Redirection Table entry to point
- * to the given IDT vector/index.
- */
-static inline void co_apic_set(int entry, int irq)
-{
-       co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
-       co_apic_write(CO_APIC_HI(entry), 0);
-}
-
-/*
- * Cobalt (IO)-APIC functions to handle PCI devices.
- */
-static inline int co_apic_ide0_hack(void)
-{
-       extern char visws_board_type;
-       extern char visws_board_rev;
-
-       if (visws_board_type == VISWS_320 && visws_board_rev == 5)
-               return 5;
-       return CO_APIC_IDE0;
-}
-
-static int is_co_apic(unsigned int irq)
-{
-       if (IS_CO_APIC(irq))
-               return CO_APIC(irq);
-
-       switch (irq) {
-               case 0: return CO_APIC_CPU;
-               case CO_IRQ_IDE0: return co_apic_ide0_hack();
-               case CO_IRQ_IDE1: return CO_APIC_IDE1;
-               default: return -1;
-       }
-}
-
-
-/*
- * This is the SGI Cobalt (IO-)APIC:
- */
-
-static void enable_cobalt_irq(unsigned int irq)
-{
-       co_apic_set(is_co_apic(irq), irq);
-}
-
-static void disable_cobalt_irq(unsigned int irq)
-{
-       int entry = is_co_apic(irq);
-
-       co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
-       co_apic_read(CO_APIC_LO(entry));
-}
-
-/*
- * "irq" really just serves to identify the device.  Here is where we
- * map this to the Cobalt APIC entry where it's physically wired.
- * This is called via request_irq -> setup_irq -> irq_desc->startup()
- */
-static unsigned int startup_cobalt_irq(unsigned int irq)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&cobalt_lock, flags);
-       if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
-               irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
-       enable_cobalt_irq(irq);
-       spin_unlock_irqrestore(&cobalt_lock, flags);
-       return 0;
-}
-
-static void ack_cobalt_irq(unsigned int irq)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&cobalt_lock, flags);
-       disable_cobalt_irq(irq);
-       apic_write(APIC_EOI, APIC_EIO_ACK);
-       spin_unlock_irqrestore(&cobalt_lock, flags);
-}
-
-static void end_cobalt_irq(unsigned int irq)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&cobalt_lock, flags);
-       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-               enable_cobalt_irq(irq);
-       spin_unlock_irqrestore(&cobalt_lock, flags);
-}
-
-static struct irq_chip cobalt_irq_type = {
-       .typename =     "Cobalt-APIC",
-       .startup =      startup_cobalt_irq,
-       .shutdown =     disable_cobalt_irq,
-       .enable =       enable_cobalt_irq,
-       .disable =      disable_cobalt_irq,
-       .ack =          ack_cobalt_irq,
-       .end =          end_cobalt_irq,
-};
-
-
-/*
- * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
- * -- not the manner expected by the code in i8259.c.
- *
- * there is a 'master' physical interrupt source that gets sent to
- * the CPU. But in the chipset there are various 'virtual' interrupts
- * waiting to be handled. We represent this to Linux through a 'master'
- * interrupt controller type, and through a special virtual interrupt-
- * controller. Device drivers only see the virtual interrupt sources.
- */
-static unsigned int startup_piix4_master_irq(unsigned int irq)
-{
-       init_8259A(0);
-
-       return startup_cobalt_irq(irq);
-}
-
-static void end_piix4_master_irq(unsigned int irq)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&cobalt_lock, flags);
-       enable_cobalt_irq(irq);
-       spin_unlock_irqrestore(&cobalt_lock, flags);
-}
-
-static struct irq_chip piix4_master_irq_type = {
-       .typename =     "PIIX4-master",
-       .startup =      startup_piix4_master_irq,
-       .ack =          ack_cobalt_irq,
-       .end =          end_piix4_master_irq,
-};
-
-
-static struct irq_chip piix4_virtual_irq_type = {
-       .typename =     "PIIX4-virtual",
-       .shutdown =     disable_8259A_irq,
-       .enable =       enable_8259A_irq,
-       .disable =      disable_8259A_irq,
-};
-
-
-/*
- * PIIX4-8259 master/virtual functions to handle interrupt requests
- * from legacy devices: floppy, parallel, serial, rtc.
- *
- * None of these get Cobalt APIC entries, neither do they have IDT
- * entries. These interrupts are purely virtual and distributed from
- * the 'master' interrupt source: CO_IRQ_8259.
- *
- * When the 8259 interrupts its handler figures out which of these
- * devices is interrupting and dispatches to its handler.
- *
- * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
- * enable_irq gets the right irq. This 'master' irq is never directly
- * manipulated by any driver.
- */
-static irqreturn_t piix4_master_intr(int irq, void *dev_id)
-{
-       int realirq;
-       irq_desc_t *desc;
-       unsigned long flags;
-
-       spin_lock_irqsave(&i8259A_lock, flags);
-
-       /* Find out what's interrupting in the PIIX4 master 8259 */
-       outb(0x0c, 0x20);               /* OCW3 Poll command */
-       realirq = inb(0x20);
-
-       /*
-        * Bit 7 == 0 means invalid/spurious
-        */
-       if (unlikely(!(realirq & 0x80)))
-               goto out_unlock;
-
-       realirq &= 7;
-
-       if (unlikely(realirq == 2)) {
-               outb(0x0c, 0xa0);
-               realirq = inb(0xa0);
-
-               if (unlikely(!(realirq & 0x80)))
-                       goto out_unlock;
-
-               realirq = (realirq & 7) + 8;
-       }
-
-       /* mask and ack interrupt */
-       cached_irq_mask |= 1 << realirq;
-       if (unlikely(realirq > 7)) {
-               inb(0xa1);
-               outb(cached_slave_mask, 0xa1);
-               outb(0x60 + (realirq & 7), 0xa0);
-               outb(0x60 + 2, 0x20);
-       } else {
-               inb(0x21);
-               outb(cached_master_mask, 0x21);
-               outb(0x60 + realirq, 0x20);
-       }
-
-       spin_unlock_irqrestore(&i8259A_lock, flags);
-
-       desc = irq_desc + realirq;
-
-       /*
-        * handle this 'virtual interrupt' as a Cobalt one now.
-        */
-       kstat_cpu(smp_processor_id()).irqs[realirq]++;
-
-       if (likely(desc->action != NULL))
-               handle_IRQ_event(realirq, desc->action);
-
-       if (!(desc->status & IRQ_DISABLED))
-               enable_8259A_irq(realirq);
-
-       return IRQ_HANDLED;
-
-out_unlock:
-       spin_unlock_irqrestore(&i8259A_lock, flags);
-       return IRQ_NONE;
-}
-
-static struct irqaction master_action = {
-       .handler =      piix4_master_intr,
-       .name =         "PIIX4-8259",
-};
-
-static struct irqaction cascade_action = {
-       .handler =      no_action,
-       .name =         "cascade",
-};
-
-
-void init_VISWS_APIC_irqs(void)
-{
-       int i;
-
-       for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
-               irq_desc[i].status = IRQ_DISABLED;
-               irq_desc[i].action = 0;
-               irq_desc[i].depth = 1;
-
-               if (i == 0) {
-                       irq_desc[i].chip = &cobalt_irq_type;
-               }
-               else if (i == CO_IRQ_IDE0) {
-                       irq_desc[i].chip = &cobalt_irq_type;
-               }
-               else if (i == CO_IRQ_IDE1) {
-                       irq_desc[i].chip = &cobalt_irq_type;
-               }
-               else if (i == CO_IRQ_8259) {
-                       irq_desc[i].chip = &piix4_master_irq_type;
-               }
-               else if (i < CO_IRQ_APIC0) {
-                       irq_desc[i].chip = &piix4_virtual_irq_type;
-               }
-               else if (IS_CO_APIC(i)) {
-                       irq_desc[i].chip = &cobalt_irq_type;
-               }
-       }
-
-       setup_irq(CO_IRQ_8259, &master_action);
-       setup_irq(2, &cascade_action);
-}
diff --git a/arch/x86/kernel/traps_visws.c b/arch/x86/kernel/traps_visws.c
deleted file mode 100644 (file)
index e5e6492..0000000
+++ /dev/null
@@ -1,71 +0,0 @@
-/* VISWS traps */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/pci_ids.h>
-
-#include <asm/io.h>
-#include <asm/apic.h>
-#include <asm/arch_hooks.h>
-#include <asm/visws/cobalt.h>
-#include <asm/visws/lithium.h>
-
-
-#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
-#define BCD (LI_INTB | LI_INTC | LI_INTD)
-#define ALLDEVS (A01234 | BCD)
-
-static __init void lithium_init(void)
-{
-       set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
-       set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
-
-       if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
-           (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
-               printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
-/*             panic("This machine is not SGI Visual Workstation 320/540"); */
-       }
-
-       if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
-           (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
-               printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
-/*             panic("This machine is not SGI Visual Workstation 320/540"); */
-       }
-
-       li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
-       li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
-}
-
-static __init void cobalt_init(void)
-{
-       /*
-        * On normal SMP PC this is used only with SMP, but we have to
-        * use it and set it up here to start the Cobalt clock
-        */
-       set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
-       setup_local_APIC();
-       printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
-               (unsigned int)apic_read(APIC_LVR),
-               (unsigned int)apic_read(APIC_ID));
-
-       set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
-       set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
-       printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
-               co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
-
-       /* Enable Cobalt APIC being careful to NOT change the ID! */
-       co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
-
-       printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
-               co_apic_read(CO_APIC_ID));
-}
-
-int __init visws_trap_init_quirk(void)
-{
-       lithium_init();
-       cobalt_init();
-
-       return 1;
-}
index e19b91c47e9097bd8497c4c18a0a325cd898fc7a..5c715c24ab55b1a17e03a9195660f3874db71acb 100644 (file)
@@ -1,8 +1,22 @@
 /*
- *  Unmaintained SGI Visual Workstation support.
+ *  SGI Visual Workstation support and quirks, unmaintained.
+ *
  *  Split out from setup.c by davej@suse.de
+ *
+ *     Copyright (C) 1999 Bent Hagemark, Ingo Molnar
+ *
+ *  SGI Visual Workstation interrupt controller
+ *
+ *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
+ *  which serves as the main interrupt controller in the system.  Non-legacy
+ *  hardware in the system uses this controller directly.  Legacy devices
+ *  are connected to the PIIX4 which in turn has its 8259(s) connected to
+ *  a of the Cobalt APIC entry.
+ *
+ *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
+ *
+ *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
  */
-
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/init.h>
 #include <linux/smp.h>
 
+#include <linux/kernel_stat.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/apic.h>
+#include <asm/i8259.h>
+#include <asm/irq_vectors.h>
+#include <asm/visws/cobalt.h>
+#include <asm/visws/lithium.h>
+#include <asm/visws/piix4.h>
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include <asm/io.h>
+#include <asm/apic.h>
+#include <asm/arch_hooks.h>
+#include <asm/visws/cobalt.h>
+#include <asm/visws/lithium.h>
+
 char visws_board_type  = -1;
 char visws_board_rev   = -1;
 
@@ -336,3 +374,334 @@ void __init visws_early_detect(void)
               (visws_board_type == VISWS_540 ? "540" :
                "unknown")), visws_board_rev);
 }
+
+#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
+#define BCD (LI_INTB | LI_INTC | LI_INTD)
+#define ALLDEVS (A01234 | BCD)
+
+static __init void lithium_init(void)
+{
+       set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
+       set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
+
+       if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
+           (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
+               printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
+/*             panic("This machine is not SGI Visual Workstation 320/540"); */
+       }
+
+       if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
+           (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
+               printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
+/*             panic("This machine is not SGI Visual Workstation 320/540"); */
+       }
+
+       li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
+       li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
+}
+
+static __init void cobalt_init(void)
+{
+       /*
+        * On normal SMP PC this is used only with SMP, but we have to
+        * use it and set it up here to start the Cobalt clock
+        */
+       set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
+       setup_local_APIC();
+       printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
+               (unsigned int)apic_read(APIC_LVR),
+               (unsigned int)apic_read(APIC_ID));
+
+       set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
+       set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
+       printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
+               co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
+
+       /* Enable Cobalt APIC being careful to NOT change the ID! */
+       co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
+
+       printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
+               co_apic_read(CO_APIC_ID));
+}
+
+int __init visws_trap_init_quirk(void)
+{
+       lithium_init();
+       cobalt_init();
+
+       return 1;
+}
+
+/*
+ * IRQ controller / APIC support:
+ */
+
+static DEFINE_SPINLOCK(cobalt_lock);
+
+/*
+ * Set the given Cobalt APIC Redirection Table entry to point
+ * to the given IDT vector/index.
+ */
+static inline void co_apic_set(int entry, int irq)
+{
+       co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
+       co_apic_write(CO_APIC_HI(entry), 0);
+}
+
+/*
+ * Cobalt (IO)-APIC functions to handle PCI devices.
+ */
+static inline int co_apic_ide0_hack(void)
+{
+       extern char visws_board_type;
+       extern char visws_board_rev;
+
+       if (visws_board_type == VISWS_320 && visws_board_rev == 5)
+               return 5;
+       return CO_APIC_IDE0;
+}
+
+static int is_co_apic(unsigned int irq)
+{
+       if (IS_CO_APIC(irq))
+               return CO_APIC(irq);
+
+       switch (irq) {
+               case 0: return CO_APIC_CPU;
+               case CO_IRQ_IDE0: return co_apic_ide0_hack();
+               case CO_IRQ_IDE1: return CO_APIC_IDE1;
+               default: return -1;
+       }
+}
+
+
+/*
+ * This is the SGI Cobalt (IO-)APIC:
+ */
+
+static void enable_cobalt_irq(unsigned int irq)
+{
+       co_apic_set(is_co_apic(irq), irq);
+}
+
+static void disable_cobalt_irq(unsigned int irq)
+{
+       int entry = is_co_apic(irq);
+
+       co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
+       co_apic_read(CO_APIC_LO(entry));
+}
+
+/*
+ * "irq" really just serves to identify the device.  Here is where we
+ * map this to the Cobalt APIC entry where it's physically wired.
+ * This is called via request_irq -> setup_irq -> irq_desc->startup()
+ */
+static unsigned int startup_cobalt_irq(unsigned int irq)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&cobalt_lock, flags);
+       if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
+               irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
+       enable_cobalt_irq(irq);
+       spin_unlock_irqrestore(&cobalt_lock, flags);
+       return 0;
+}
+
+static void ack_cobalt_irq(unsigned int irq)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&cobalt_lock, flags);
+       disable_cobalt_irq(irq);
+       apic_write(APIC_EOI, APIC_EIO_ACK);
+       spin_unlock_irqrestore(&cobalt_lock, flags);
+}
+
+static void end_cobalt_irq(unsigned int irq)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&cobalt_lock, flags);
+       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+               enable_cobalt_irq(irq);
+       spin_unlock_irqrestore(&cobalt_lock, flags);
+}
+
+static struct irq_chip cobalt_irq_type = {
+       .typename =     "Cobalt-APIC",
+       .startup =      startup_cobalt_irq,
+       .shutdown =     disable_cobalt_irq,
+       .enable =       enable_cobalt_irq,
+       .disable =      disable_cobalt_irq,
+       .ack =          ack_cobalt_irq,
+       .end =          end_cobalt_irq,
+};
+
+
+/*
+ * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
+ * -- not the manner expected by the code in i8259.c.
+ *
+ * there is a 'master' physical interrupt source that gets sent to
+ * the CPU. But in the chipset there are various 'virtual' interrupts
+ * waiting to be handled. We represent this to Linux through a 'master'
+ * interrupt controller type, and through a special virtual interrupt-
+ * controller. Device drivers only see the virtual interrupt sources.
+ */
+static unsigned int startup_piix4_master_irq(unsigned int irq)
+{
+       init_8259A(0);
+
+       return startup_cobalt_irq(irq);
+}
+
+static void end_piix4_master_irq(unsigned int irq)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&cobalt_lock, flags);
+       enable_cobalt_irq(irq);
+       spin_unlock_irqrestore(&cobalt_lock, flags);
+}
+
+static struct irq_chip piix4_master_irq_type = {
+       .typename =     "PIIX4-master",
+       .startup =      startup_piix4_master_irq,
+       .ack =          ack_cobalt_irq,
+       .end =          end_piix4_master_irq,
+};
+
+
+static struct irq_chip piix4_virtual_irq_type = {
+       .typename =     "PIIX4-virtual",
+       .shutdown =     disable_8259A_irq,
+       .enable =       enable_8259A_irq,
+       .disable =      disable_8259A_irq,
+};
+
+
+/*
+ * PIIX4-8259 master/virtual functions to handle interrupt requests
+ * from legacy devices: floppy, parallel, serial, rtc.
+ *
+ * None of these get Cobalt APIC entries, neither do they have IDT
+ * entries. These interrupts are purely virtual and distributed from
+ * the 'master' interrupt source: CO_IRQ_8259.
+ *
+ * When the 8259 interrupts its handler figures out which of these
+ * devices is interrupting and dispatches to its handler.
+ *
+ * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
+ * enable_irq gets the right irq. This 'master' irq is never directly
+ * manipulated by any driver.
+ */
+static irqreturn_t piix4_master_intr(int irq, void *dev_id)
+{
+       int realirq;
+       irq_desc_t *desc;
+       unsigned long flags;
+
+       spin_lock_irqsave(&i8259A_lock, flags);
+
+       /* Find out what's interrupting in the PIIX4 master 8259 */
+       outb(0x0c, 0x20);               /* OCW3 Poll command */
+       realirq = inb(0x20);
+
+       /*
+        * Bit 7 == 0 means invalid/spurious
+        */
+       if (unlikely(!(realirq & 0x80)))
+               goto out_unlock;
+
+       realirq &= 7;
+
+       if (unlikely(realirq == 2)) {
+               outb(0x0c, 0xa0);
+               realirq = inb(0xa0);
+
+               if (unlikely(!(realirq & 0x80)))
+                       goto out_unlock;
+
+               realirq = (realirq & 7) + 8;
+       }
+
+       /* mask and ack interrupt */
+       cached_irq_mask |= 1 << realirq;
+       if (unlikely(realirq > 7)) {
+               inb(0xa1);
+               outb(cached_slave_mask, 0xa1);
+               outb(0x60 + (realirq & 7), 0xa0);
+               outb(0x60 + 2, 0x20);
+       } else {
+               inb(0x21);
+               outb(cached_master_mask, 0x21);
+               outb(0x60 + realirq, 0x20);
+       }
+
+       spin_unlock_irqrestore(&i8259A_lock, flags);
+
+       desc = irq_desc + realirq;
+
+       /*
+        * handle this 'virtual interrupt' as a Cobalt one now.
+        */
+       kstat_cpu(smp_processor_id()).irqs[realirq]++;
+
+       if (likely(desc->action != NULL))
+               handle_IRQ_event(realirq, desc->action);
+
+       if (!(desc->status & IRQ_DISABLED))
+               enable_8259A_irq(realirq);
+
+       return IRQ_HANDLED;
+
+out_unlock:
+       spin_unlock_irqrestore(&i8259A_lock, flags);
+       return IRQ_NONE;
+}
+
+static struct irqaction master_action = {
+       .handler =      piix4_master_intr,
+       .name =         "PIIX4-8259",
+};
+
+static struct irqaction cascade_action = {
+       .handler =      no_action,
+       .name =         "cascade",
+};
+
+
+void init_VISWS_APIC_irqs(void)
+{
+       int i;
+
+       for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
+               irq_desc[i].status = IRQ_DISABLED;
+               irq_desc[i].action = 0;
+               irq_desc[i].depth = 1;
+
+               if (i == 0) {
+                       irq_desc[i].chip = &cobalt_irq_type;
+               }
+               else if (i == CO_IRQ_IDE0) {
+                       irq_desc[i].chip = &cobalt_irq_type;
+               }
+               else if (i == CO_IRQ_IDE1) {
+                       irq_desc[i].chip = &cobalt_irq_type;
+               }
+               else if (i == CO_IRQ_8259) {
+                       irq_desc[i].chip = &piix4_master_irq_type;
+               }
+               else if (i < CO_IRQ_APIC0) {
+                       irq_desc[i].chip = &piix4_virtual_irq_type;
+               }
+               else if (IS_CO_APIC(i)) {
+                       irq_desc[i].chip = &cobalt_irq_type;
+               }
+       }
+
+       setup_irq(CO_IRQ_8259, &master_action);
+       setup_irq(2, &cascade_action);
+}