};
} // end anonymous namespace
+namespace llvm {
+ // FIXME: TableGen this?
+ extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
+}
+
namespace {
/// ARMOperand - Instances of this class represent a parsed ARM machine
SMLoc StartLoc, SMLoc EndLoc) {
KindTy Kind = RegisterList;
- if (ARM::DPRRegClass.contains(Regs.front().first))
+ if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
+ contains(Regs.front().first))
Kind = DPRRegisterList;
- else if (ARM::SPRRegClass.contains(Regs.front().first))
+ else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
+ contains(Regs.front().first))
Kind = SPRRegisterList;
ARMOperand *Op = new ARMOperand(Kind);