clk: rockchip: rk3399: Add CLK_SET_RATE_PARENT for main VOP0

We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.

Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index eddf6ec23005985d56a711de9a592a880be4ca26..ff549297ba34277297eab4ee5b362b1c53d5cb46 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1135,10 +1135,11 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(28), 0, GFLAGS),
 
-       COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
+       COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 12, GFLAGS),
 
+       /* The VOP0 is main screen, it is able to re-set parent rate. */
        COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(106), 0,
                        &rk3399_dclk_vop0_fracmux),
@@ -1165,6 +1166,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
                        RK3399_CLKGATE_CON(28), 4, GFLAGS),
 
+       /* The VOP1 is sub screen, it is note able to re-set parent rate. */
        COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
                        RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3399_CLKGATE_CON(10), 13, GFLAGS),