rk3036 hdmi: fix some define error
authorhjc <hjc@rock-chips.com>
Fri, 4 Jul 2014 09:37:07 +0000 (17:37 +0800)
committerhjc <hjc@rock-chips.com>
Mon, 7 Jul 2014 03:13:03 +0000 (11:13 +0800)
drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.c
drivers/video/rockchip/hdmi/chips/rk616/rk616_hdmi_hw.h

index 26d91496d974cdb6c5b0edf9af1ec30c9599b381..7948608899a5f839cfaca2bac0591f9742e1175c 100755 (executable)
@@ -130,15 +130,15 @@ static void rk616_hdmi_set_pwr_mode(struct hdmi *hdmi_drv, int mode)
                        hdmi_writel(hdmi_dev, PHY_DRIVER, 0x99);
                        hdmi_writel(hdmi_dev, PHY_PRE_EMPHASIS, 0x0f);
                }
-#ifndef SOC_CONFIG_RK3036
+#ifdef SOC_CONFIG_RK3036
+               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x15);
+               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x14);
+               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x10);
+#else
                hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x2d);
                hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x2c);
                hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x28);
                hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x20);
-#else
-               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x15);
-               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x14);
-               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x10);
 #endif
                hdmi_writel(hdmi_dev, PHY_CHG_PWR, 0x0f);
                hdmi_writel(hdmi_dev, 0xce, 0x00);
@@ -155,10 +155,10 @@ static void rk616_hdmi_set_pwr_mode(struct hdmi *hdmi_drv, int mode)
                hdmi_writel(hdmi_dev, PHY_DRIVER, 0x00);
                hdmi_writel(hdmi_dev, PHY_PRE_EMPHASIS, 0x00);
                hdmi_writel(hdmi_dev, PHY_CHG_PWR, 0x00);
-#ifndef SOC_CONFIG_RK3036
-               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x2f);
-#else
+#ifdef SOC_CONFIG_RK3036
                hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x17);
+#else
+               hdmi_writel(hdmi_dev, PHY_SYS_CTL,0x2f);
 #endif
                break;
        default:
@@ -270,10 +270,10 @@ int rk616_hdmi_read_edid(struct hdmi *hdmi_drv, int block, u8 *buf)
                }
        }
        //close edid irq
-#ifndef SOC_CONFIG_RK3036
-        hdmi_writel(hdmi_dev, INTERRUPT_MASK1, m_INT_HOTPLUG);
-#else
+#ifdef SOC_CONFIG_RK3036
        hdmi_writel(hdmi_dev, INTERRUPT_MASK1, 0);
+#else
+       hdmi_writel(hdmi_dev, INTERRUPT_MASK1, m_INT_HOTPLUG);
 #endif
        enable_irq(hdmi_drv->irq);
 
@@ -583,17 +583,16 @@ void rk616_hdmi_work(struct hdmi *hdmi_drv)
        struct rk_hdmi_device *hdmi_dev = container_of(hdmi_drv,
                                                       struct rk_hdmi_device,
                                                       driver);
-
-#ifndef SOC_CONFIG_RK3036
-        hdmi_readl(hdmi_dev, INTERRUPT_STATUS1,&interrupt);
-        if(interrupt){
-                hdmi_writel(hdmi_dev, INTERRUPT_STATUS1, interrupt);
-        }
-#else
+#ifdef SOC_CONFIG_RK3036
        hdmi_readl(hdmi_dev, HDMI_STATUS,&interrupt);
        if(interrupt){
                hdmi_writel(hdmi_dev, HDMI_STATUS, interrupt);
        }
+#else
+       hdmi_readl(hdmi_dev, INTERRUPT_STATUS1,&interrupt);
+       if(interrupt){
+               hdmi_writel(hdmi_dev, INTERRUPT_STATUS1, interrupt);
+       }
 #endif
        if (interrupt & m_HOTPLUG) {
                if (hdmi_drv->state == HDMI_SLEEP)
@@ -623,12 +622,12 @@ static void rk616_hdmi_reset(struct hdmi *hdmi_drv)
        msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
        val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
        hdmi_msk_reg(hdmi_dev, SYS_CTRL, msk, val);
-#ifndef SOC_CONFIG_RK3036
-       hdmi_writel(hdmi_dev, INTERRUPT_MASK1, m_INT_HOTPLUG);
-#else
+#ifdef SOC_CONFIG_RK3036
        hdmi_readl(hdmi_dev, HDMI_STATUS,&val);//enable hpg
        val |= m_MASK_INT_HOTPLUG;
        hdmi_writel(hdmi_dev, HDMI_STATUS,val);
+#else
+       hdmi_writel(hdmi_dev, INTERRUPT_MASK1, m_INT_HOTPLUG);  
 #endif
        rk616_hdmi_set_pwr_mode(hdmi_drv, LOWER_PWR);
 }
index 41c88e6b07206822fc32ea3dc57202281915526f..83dbce3725e626b96b44ad173a679337ca347eb5 100755 (executable)
@@ -225,9 +225,9 @@ enum {
 
 #define INTERRUPT_MASK1                        0xc0
 #define INTERRUPT_STATUS1              0xc1
-       #ifndef SOC_CONFIG_RK3036
+#ifndef SOC_CONFIG_RK3036
 #define m_INT_HOTPLUG          (1 << 7)
-       #endif
+#endif
 #define        m_INT_ACTIVE_VSYNC      (1 << 5)
 #define m_INT_EDID_READY       (1 << 2)
 
@@ -239,12 +239,12 @@ enum {
 
 #define HDMI_STATUS                    0xc8
        #define m_HOTPLUG       (1 << 7)
-       #ifndef SOC_CONFIG_RK3036
-       #define m_DDC_SDA       (1 << 5)
-       #define m_DDC_SDC       (1 << 4)
-       #else
+       #ifdef SOC_CONFIG_RK3036
        #define m_MASK_INT_HOTPLUG      (1 << 5)
        #define m_INT_HOTPLUG           (1 << 1)
+       #else
+       #define m_DDC_SDA       (1 << 5)
+       #define m_DDC_SDC       (1 << 4)        
        #endif