rk3066B: compatible with rk3188 plus pll config, fix compile error

diff --git a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
index bd7ea8e36dfd95ebdb1fdff4a4dd314b017b8d40..f9da1ab20434b791b57994efd7905434fceb7d3b 100755 (executable)
--- a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
+++ b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
@@ -71,19 +71,16 @@ enum rk_plls_id {
 #define PLL_CLKF_SET(val)      (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
 
 /*******************PLL CON2 BITS***************************/
-#if 0
-#define PLL_BWADJ_MSK          (0xfff)
+// "BWADJ" Just compatible with RK3188 plus
+#define PLL_BWADJ_MSK          (0xfff & 0x000)
 #define PLL_BWADJ_SHIFT                (0)
 #define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
-#endif
 /*******************PLL CON3 BITS***************************/
-
-#if 0
-#define PLL_REST_MSK           (1 << 5)
-#define PLL_REST_W_MSK         (PLL_REST_MSK << 16)
-#define PLL_REST               (1 << 5)
-#define PLL_REST_RESM          (0 << 5)
-#endif
+// "RESET" Just compatible with RK3188 plus
+#define PLL_RESET_MSK          ((1 & 0x0) << 5)
+#define PLL_RESET_W_MSK                (PLL_RESET_MSK << 16)
+#define PLL_RESET              (1 << 5)
+#define PLL_RESET_RESUME       (0 << 5)
 
 #define PLL_BYPASS_MSK         (1 << 0)
 #define PLL_BYPASS             (1 << 0)