bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
- let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
let Inst{11-0} = imm;
}
}
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
- let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let isCommutable = Commutable;
- let Inst{3-0} = Rm;
- let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
+ let Inst{11-4} = 0b00000000;
+ let Inst{3-0} = Rm;
}
def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
iis, opc, "\t$Rd, $Rn, $shift",
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
- let Inst{11-0} = shift;
- let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
+ let Inst{11-0} = shift;
}
}
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
- let Inst{15-12} = Rd;
+ let Inst{20} = 1;
let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
let Inst{11-0} = imm;
- let Inst{20} = 1;
}
def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
iir, opc, "\t$Rd, $Rn, $Rm",
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
- let Inst{11-4} = 0b00000000;
- let Inst{25} = 0;
let isCommutable = Commutable;
- let Inst{3-0} = Rm;
- let Inst{15-12} = Rd;
- let Inst{19-16} = Rn;
+ let Inst{25} = 0;
let Inst{20} = 1;
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
+ let Inst{11-4} = 0b00000000;
+ let Inst{3-0} = Rm;
}
def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
iis, opc, "\t$Rd, $Rn, $shift",
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
- let Inst{11-0} = shift;
- let Inst{15-12} = Rd;
- let Inst{19-16} = Rn;
let Inst{20} = 1;
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
+ let Inst{11-0} = shift;
}
}
}
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
- let Inst{15-12} = 0b0000;
+ let Inst{20} = 1;
let Inst{19-16} = Rn;
+ let Inst{15-12} = 0b0000;
let Inst{11-0} = imm;
- let Inst{20} = 1;
- let Inst{20} = 1;
}
def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
opc, "\t$Rn, $Rm",
[(opnode GPR:$Rn, GPR:$Rm)]> {
bits<4> Rn;
bits<4> Rm;
- let Inst{11-4} = 0b00000000;
- let Inst{25} = 0;
let isCommutable = Commutable;
- let Inst{3-0} = Rm;
- let Inst{15-12} = 0b0000;
- let Inst{19-16} = Rn;
+ let Inst{25} = 0;
let Inst{20} = 1;
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = 0b0000;
+ let Inst{11-4} = 0b00000000;
+ let Inst{3-0} = Rm;
}
def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
opc, "\t$Rn, $shift",
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
- let Inst{11-0} = shift;
- let Inst{15-12} = 0b0000;
- let Inst{19-16} = Rn;
let Inst{20} = 1;
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = 0b0000;
+ let Inst{11-0} = shift;
}
}
}
Requires<[IsARM, HasV6]> {
bits<4> Rd;
bits<4> Rm;
+ let Inst{19-16} = 0b1111;
let Inst{15-12} = Rd;
- let Inst{3-0} = Rm;
let Inst{11-10} = 0b00;
- let Inst{19-16} = 0b1111;
+ let Inst{3-0} = Rm;
}
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
bits<4> Rd;
bits<4> Rm;
bits<2> rot;
+ let Inst{19-16} = 0b1111;
let Inst{15-12} = Rd;
let Inst{11-10} = rot;
let Inst{3-0} = Rm;
- let Inst{19-16} = 0b1111;
}
}
IIC_iEXTr, opc, "\t$Rd, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
- let Inst{11-10} = 0b00;
let Inst{19-16} = 0b1111;
+ let Inst{11-10} = 0b00;
}
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
bits<2> rot;
- let Inst{11-10} = rot;
let Inst{19-16} = 0b1111;
+ let Inst{11-10} = rot;
}
}