#define RGA_TEST_FLUSH_TIME 0\r
#define RGA_INFO_BUS_ERROR 0\r
\r
-\r
-\r
#define PRE_SCALE_BUF_SIZE 2048*1024*4\r
\r
#define RGA_POWER_OFF_DELAY 4*HZ /* 4s */\r
if (rga_service.enable)\r
return;\r
\r
- spin_lock_bh(&rga_service.lock);\r
+ spin_lock_bh(&rga_service.lock_power);\r
clk_enable(aclk_rga);\r
clk_enable(hclk_rga);\r
rga_service.enable = true;\r
- spin_unlock_bh(&rga_service.lock);\r
+ spin_unlock_bh(&rga_service.lock_power);\r
}\r
\r
\r
static void rga_power_off(void)\r
{\r
int total_running;\r
- \r
+\r
+ spin_lock_bh(&rga_service.lock_power); \r
if(!rga_service.enable)\r
+ {\r
+ spin_unlock_bh(&rga_service.lock_power);\r
return;\r
+ }\r
\r
rga_service.enable = false;\r
\r
\r
clk_disable(aclk_rga);\r
clk_disable(hclk_rga);\r
+ spin_unlock_bh(&rga_service.lock_power);\r
\r
}\r
\r
\r
//check src_vir_w\r
if(unlikely(req->src.vir_w < req->src.act_w)){\r
- ERR("invalid src_vir_w\n");\r
+ ERR("invalid src_vir_w act_w = %d, vir_w = %d\n", req->src.act_w, req->src.vir_w);\r
return -EINVAL;\r
}\r
\r
//check dst_vir_w\r
if(unlikely(req->dst.vir_w < req->dst.act_w)){\r
- ERR("invalid dst_vir_w\n");\r
+ ERR("invalid dst_vir_w act_h = %d, vir_h = %d\n", req->dst.act_w, req->dst.vir_w);\r
return -EINVAL;\r
}\r
\r
return -ENOMEM;\r
}\r
\r
- session->pid = current->pid;\r
+ session->pid = current->pid;\r
INIT_LIST_HEAD(&session->waiting);\r
INIT_LIST_HEAD(&session->running);\r
INIT_LIST_HEAD(&session->list_session);\r
INIT_LIST_HEAD(&rga_service.done);\r
INIT_LIST_HEAD(&rga_service.session);\r
spin_lock_init(&rga_service.lock);\r
+ spin_lock_init(&rga_service.lock_power);\r
atomic_set(&rga_service.total_running, 0);\r
atomic_set(&rga_service.src_format_swt, 0);\r
rga_service.last_prc_src_format = 1; /* default is yuv first*/\r
void rga_test_1(void);\r
\r
\r
-\r
static int __init rga_init(void)\r
{\r
int ret;\r
fb = rk_get_fb(0);\r
\r
memset(&req, 0, sizeof(struct rga_req));\r
- src = src_buf;\r
+ src = Y4200_320_240_swap0;\r
dst = dst_buf;\r
\r
- memset(src_buf, 0x80, 1920*1080*4);\r
+ //memset(src_buf, 0x80, 1920*1080*4);\r
\r
- dmac_flush_range(&src_buf[0], &src_buf[1920*1080]);\r
- outer_flush_range(virt_to_phys(&src_buf[0]),virt_to_phys(&src_buf[1024*1024]));\r
+ //dmac_flush_range(&src_buf[0], &src_buf[1920*1080]);\r
+ //outer_flush_range(virt_to_phys(&src_buf[0]),virt_to_phys(&src_buf[1024*1024]));\r
\r
#if 0\r
memset(src_buf, 0x80, 800*480*4);\r
outer_flush_range(virt_to_phys(&dst_buf[0]),virt_to_phys(&dst_buf[800*480]));\r
#endif\r
\r
- req.src.act_w = 1920;\r
- req.src.act_h = 1080;\r
+ req.src.act_w = 320;\r
+ req.src.act_h = 240;\r
\r
- req.src.vir_w = 1920;\r
- req.src.vir_h = 1080;\r
- req.src.yrgb_addr = (uint32_t)virt_to_phys(src_buf);\r
- req.src.uv_addr = req.src.yrgb_addr + 1920;\r
- //req.src.v_addr = (uint32_t)V4200_320_240_swap0;\r
- req.src.format = RK_FORMAT_RGB_565;\r
+ req.src.vir_w = 320;\r
+ req.src.vir_h = 240;\r
+ req.src.yrgb_addr = (uint32_t)src;\r
+ req.src.uv_addr = (uint32_t)UV4200_320_240_swap0;\r
+ req.src.v_addr = (uint32_t)V4200_320_240_swap0;\r
+ req.src.format = RK_FORMAT_YCbCr_420_SP;\r
\r
- req.dst.act_w = 1024;\r
- req.dst.act_h = 768;\r
+ req.dst.act_w = 1280;\r
+ req.dst.act_h = 800;\r
\r
req.dst.vir_w = 1280;\r
req.dst.vir_h = 800;\r
req.dst.x_offset = 0;\r
req.dst.y_offset = 0;\r
- req.dst.yrgb_addr = (uint32_t)virt_to_phys(dst);\r
+ req.dst.yrgb_addr = (uint32_t)dst;\r
\r
- req.dst.format = RK_FORMAT_RGB_565;\r
+ //req.dst.format = RK_FORMAT_RGB_565;\r
\r
req.clip.xmin = 0;\r
req.clip.xmax = 1279;\r
//req.fg_color = 0x80ffffff;\r
\r
req.rotate_mode = 1;\r
- req.scale_mode = 1;\r
+ req.scale_mode = 2;\r
\r
- req.alpha_rop_flag = 0;\r
- req.alpha_rop_mode = 0x1;\r
+ //req.alpha_rop_flag = 0;\r
+ //req.alpha_rop_mode = 0x1;\r
\r
req.sina = 0;\r
req.cosa = 65536;\r
\r
- req.mmu_info.mmu_flag = 0x0;\r
- req.mmu_info.mmu_en = 0;\r
+ req.mmu_info.mmu_flag = 0x21;\r
+ req.mmu_info.mmu_en = 1;\r
\r
rga_blit_sync(&session, &req);\r
\r