video: tegra: support v/h sync polarity
authorErik Gilling <konkers@android.com>
Wed, 2 Feb 2011 20:12:31 +0000 (12:12 -0800)
committerErik Gilling <konkers@android.com>
Thu, 3 Feb 2011 02:36:55 +0000 (18:36 -0800)
Change-Id: Ida82a70efaeadc9d5b11d8703e688063680b72a8
Signed-off-by: Erik Gilling <konkers@android.com>
arch/arm/mach-tegra/include/mach/dc.h
drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_reg.h
drivers/video/tegra/fb.c

index 43a9ec1e141d8b6d47add2934ad8e32b1159308c..9fe8d6a7e71b8bdd40e289705db85ce96c0704b5 100644 (file)
@@ -37,8 +37,12 @@ struct tegra_dc_mode {
        int     v_active;
        int     h_front_porch;
        int     v_front_porch;
+       u32     flags;
 };
 
+#define TEGRA_DC_MODE_FLAG_NEG_V_SYNC  (1 << 0)
+#define TEGRA_DC_MODE_FLAG_NEG_H_SYNC  (1 << 1)
+
 enum {
        TEGRA_DC_OUT_RGB,
        TEGRA_DC_OUT_HDMI,
index c57a8f9ded4f5e6c81ac0fbb447fc2e057b8d438..d316fde01662de135db2dae78b8f91122f0d8098 100644 (file)
@@ -736,6 +736,18 @@ static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode
        tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
                        DC_DISP_DATA_ENABLE_OPTIONS);
 
+       val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
+       if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
+               val |= PIN1_LVS_OUTPUT;
+       else
+               val &= ~PIN1_LVS_OUTPUT;
+
+       if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
+               val |= PIN1_LHS_OUTPUT;
+       else
+               val &= ~PIN1_LHS_OUTPUT;
+       tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
+
        /* TODO: MIPI/CRT/HDMI clock cals */
 
        val = DISP_DATA_FORMAT_DF1P1C;
index bd1750b78e448c57312a12dc534379e565f5512d..ab21c6eba0e169fa98661c11402859fc650b4204 100644 (file)
 #define DC_COM_PIN_OUTPUT_SELECT4              0x318
 #define DC_COM_PIN_OUTPUT_SELECT5              0x319
 #define DC_COM_PIN_OUTPUT_SELECT6              0x31a
+
+#define  PIN1_LHS_OUTPUT               (1 << 30)
+#define  PIN1_LVS_OUTPUT               (1 << 28)
+
 #define DC_COM_PIN_MISC_CONTROL                        0x31b
 #define DC_COM_PM0_CONTROL                     0x31c
 #define DC_COM_PM0_DUTY_CYCLE                  0x31d
index 5d6a11a4ba55f58ef781148e3f314ed0ef2068ed..4f8a5c0270f7a71ca4ccc4418959c3f9e8eab61c 100644 (file)
@@ -194,6 +194,14 @@ static int tegra_fb_set_par(struct fb_info *info)
                mode.h_front_porch = info->mode->right_margin;
                mode.v_front_porch = info->mode->lower_margin;
 
+               mode.flags = 0;
+
+               if (!(info->mode->sync & FB_SYNC_HOR_HIGH_ACT))
+                       mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
+
+               if (!(info->mode->sync & FB_SYNC_VERT_HIGH_ACT))
+                       mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
+
                tegra_dc_set_mode(tegra_fb->win->dc, &mode);
 
                tegra_fb->win->w = info->mode->xres;