int v_active;
int h_front_porch;
int v_front_porch;
+ u32 flags;
};
+#define TEGRA_DC_MODE_FLAG_NEG_V_SYNC (1 << 0)
+#define TEGRA_DC_MODE_FLAG_NEG_H_SYNC (1 << 1)
+
enum {
TEGRA_DC_OUT_RGB,
TEGRA_DC_OUT_HDMI,
tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
DC_DISP_DATA_ENABLE_OPTIONS);
+ val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
+ if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
+ val |= PIN1_LVS_OUTPUT;
+ else
+ val &= ~PIN1_LVS_OUTPUT;
+
+ if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
+ val |= PIN1_LHS_OUTPUT;
+ else
+ val &= ~PIN1_LHS_OUTPUT;
+ tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
+
/* TODO: MIPI/CRT/HDMI clock cals */
val = DISP_DATA_FORMAT_DF1P1C;
#define DC_COM_PIN_OUTPUT_SELECT4 0x318
#define DC_COM_PIN_OUTPUT_SELECT5 0x319
#define DC_COM_PIN_OUTPUT_SELECT6 0x31a
+
+#define PIN1_LHS_OUTPUT (1 << 30)
+#define PIN1_LVS_OUTPUT (1 << 28)
+
#define DC_COM_PIN_MISC_CONTROL 0x31b
#define DC_COM_PM0_CONTROL 0x31c
#define DC_COM_PM0_DUTY_CYCLE 0x31d
mode.h_front_porch = info->mode->right_margin;
mode.v_front_porch = info->mode->lower_margin;
+ mode.flags = 0;
+
+ if (!(info->mode->sync & FB_SYNC_HOR_HIGH_ACT))
+ mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
+
+ if (!(info->mode->sync & FB_SYNC_VERT_HIGH_ACT))
+ mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
+
tegra_dc_set_mode(tegra_fb->win->dc, &mode);
tegra_fb->win->w = info->mode->xres;