e1000e: enable new 82567V-3 device
authorBruce Allan <bruce.w.allan@intel.com>
Tue, 1 Dec 2009 15:50:31 +0000 (15:50 +0000)
committerGreg Kroah-Hartman <gregkh@suse.de>
Thu, 1 Apr 2010 22:58:17 +0000 (15:58 -0700)
commit 9e135a2e6266eba276f33c404a2478499bc07ff5 upstream.

This new PCI device ID is for a new combination of MAC and PHY both of
which already have supporting code in the driver, just not yet in this
combination.  During validation of the device, an intermittent issue was
discovered with waking it from a suspended state which can be resolved with
the pre-existing workaround to disable gigabit speed prior to suspending.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
drivers/net/e1000e/hw.h
drivers/net/e1000e/ich8lan.c
drivers/net/e1000e/netdev.c

index aaea41ef794dc1ee1fe23d124a4192b058e146e5..e8e87a723fada3a24da353d1938b7c974b203aae 100644 (file)
@@ -356,6 +356,7 @@ enum e1e_registers {
 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT    0x10BA
 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT    0x10BB
 
+#define E1000_DEV_ID_ICH8_82567V_3             0x1501
 #define E1000_DEV_ID_ICH8_IGP_M_AMT            0x1049
 #define E1000_DEV_ID_ICH8_IGP_AMT              0x104A
 #define E1000_DEV_ID_ICH8_IGP_C                        0x104B
index eff3f478365556bf00a5ed996a398bf051190105..c688b55c1b7564adc002f18a5da93bf5170f9a70 100644 (file)
@@ -3209,6 +3209,7 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
        u32 phy_ctrl;
 
        switch (hw->mac.type) {
+       case e1000_ich8lan:
        case e1000_ich9lan:
        case e1000_ich10lan:
        case e1000_pchlan:
index 21545306bc1d433d6b0decf2325f0a1481a4d3b1..f590beafca1f4c479160b753f744f26ea22aad45 100644 (file)
@@ -5360,6 +5360,7 @@ static struct pci_device_id e1000_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
 
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },