The SDHCI controller specifies a maximum SDCLK speed of 48MHz, which is
now in agreement with the platform clock, and so the SDHCI host max_clk
no longer needs to be overriden.
Change-Id: Ie8c7f643d956cfd1bb83675708336278482c40d8
Signed-off-by: Todd Poynor <toddpoynor@google.com>
return 0;
}
-static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
-{
- struct tegra_sdhci_host *tegra_host = sdhci_priv(host);
- host->max_clk = clk_get_rate(tegra_host->clk);
-}
-
static struct sdhci_ops tegra_sdhci_ops = {
.enable_dma = tegra_sdhci_enable_dma,
- .set_clock = tegra_sdhci_set_clock,
};
static int __devinit tegra_sdhci_probe(struct platform_device *pdev)