rk3288-tb: adjust clk core dvfs table; init vdd_logic by ddr dvfs table

diff --git a/arch/arm/boot/dts/rk3288-tb.dts b/arch/arm/boot/dts/rk3288-tb.dts
index ecafd2422d9ca68da44dd76e08923a642acceec6..3297386002c1d745e218454207126c82796fd7d5 100755 (executable)
--- a/arch/arm/boot/dts/rk3288-tb.dts
+++ b/arch/arm/boot/dts/rk3288-tb.dts
@@ -571,13 +571,18 @@ rockchip,power_type = <GPIO>;
 &clk_core_dvfs_table {
        operating-points = <
                /* KHz    uV */
+               126000 850000
+               216000 850000
                312000 850000
-               504000 850000
+               408000 850000
+               600000 850000
+               696000 900000
                816000 950000
                1008000 1000000
                1200000 1050000
                1416000 1150000
                >;
+       status="okay";
 };
 
 &clk_gpu_dvfs_table {
@@ -589,14 +594,16 @@ rockchip,power_type = <GPIO>;
                400000 1000000
                600000 1250000
                >;
+       status="okay";
 };
 
 &clk_ddr_dvfs_table {
        operating-points = <
                /* KHz    uV */
-               200000 1200000
-               300000 1200000
-               400000 1200000
+               200000 950000
+               300000 950000
+               400000 1000000
+               533000 1050000
                >;
 
        freq_table = <
@@ -606,6 +613,7 @@ rockchip,power_type = <GPIO>;
                SYS_STATUS_VIDEO        300000
                SYS_STATUS_DUALVIEW     500000
                >;
+       status="okay";
 };
 
 /include/ "rk808.dtsi"

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index aa3b31612a4a7eeb6e263643cf8236e4114d16e6..eaf4c1f7d352c9cbb619efbe0a7dbbc9fa4759ea 100755 (executable)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -879,7 +879,7 @@
                                                300000 1300000
                                                400000 1300000
                                                >;
-                                       status = "okay";
+                                       status = "disable";
                                };
                        };
                };

diff --git a/arch/arm/mach-rockchip/ddr_freq.c b/arch/arm/mach-rockchip/ddr_freq.c
index 3dee44c44d3ecb8eee14aeaa45a4c1f6a89bb456..43bc2e358f6b6e919cfa0f72a3e223977213dbcc 100644 (file)
--- a/arch/arm/mach-rockchip/ddr_freq.c
+++ b/arch/arm/mach-rockchip/ddr_freq.c
@@ -433,4 +433,4 @@ err:
 
        return ret;
 }
-late_initcall(ddrfreq_init);
+//late_initcall(ddrfreq_init);

diff --git a/arch/arm/mach-rockchip/dvfs.c b/arch/arm/mach-rockchip/dvfs.c
index 7e4e2e7b25e5ea9b66ec726c7e8c2c5b88e4922c..25f52fbee2cccd82848e180abb2ee3c1a9afedd0 100644 (file)
--- a/arch/arm/mach-rockchip/dvfs.c
+++ b/arch/arm/mach-rockchip/dvfs.c
@@ -633,7 +633,7 @@ int clk_enable_dvfs(struct dvfs_node *clk_dvfs_node)
                clk_dvfs_node->freq_limit_en = 1;
                dvfs_table_round_volt(clk_dvfs_node);
                clk_dvfs_node->set_freq = clk_dvfs_node_get_rate_kz(clk_dvfs_node->clk);
-               clk_dvfs_node->last_set_rate = clk_dvfs_node->set_freq;
+               clk_dvfs_node->last_set_rate = clk_dvfs_node->set_freq*1000;
                
                DVFS_DBG("%s: %s get freq %u!\n", 
                        __func__, clk_dvfs_node->name, clk_dvfs_node->set_freq);

diff --git a/arch/arm/mach-rockchip/rk3188.c b/arch/arm/mach-rockchip/rk3188.c
index 79c53e221cc48023f389e50148f00cdf236876ec..18b1dd296fb3afd1b26f6fb40e5fc8ccdc8f113c 100644 (file)
--- a/arch/arm/mach-rockchip/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188.c
@@ -371,12 +371,14 @@ static void __init rk3188_init_suspend(void)
 
 static int __init rk3188_ddr_init(void)
 {
-       ddr_change_freq = _ddr_change_freq;
-       ddr_round_rate = _ddr_round_rate;
-       ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
-       
-       if (cpu_is_rk3188())
+       if (cpu_is_rk3188()) {
+
+               ddr_change_freq = _ddr_change_freq;
+               ddr_round_rate = _ddr_round_rate;
+               ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
+
                ddr_init(DDR3_DEFAULT, 300);
+       }
 
        return 0;
 }

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 3b59e3def34ff39bc50b0906831f3aefe5676f66..8a803bd6d5cc03c57c43ce4558b234f58263ec6d 100644 (file)
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -425,7 +425,7 @@ static long clk_ddr_determine_rate(struct clk_hw *hw, unsigned long rate,
 
        if (!ddr_round_rate) {
                /* Do nothing before ddr init */
-               best = __clk_get_rate(hw->clk);
+               best = rate;//__clk_get_rate(hw->clk);
        } else {
                /* Func provided by ddr driver */
                best = ddr_round_rate(rate/MHZ) * MHZ;

diff --git a/drivers/cpufreq/rockchip-cpufreq.c b/drivers/cpufreq/rockchip-cpufreq.c
index 473ac4a480805bfe0a0a21acb51389209fa7080d..b0676fa3a04b43aab3359bc4579a2a667881cc82 100644 (file)
--- a/drivers/cpufreq/rockchip-cpufreq.c
+++ b/drivers/cpufreq/rockchip-cpufreq.c
@@ -74,6 +74,7 @@ static bool gpu_is_mali400;
 struct dvfs_node *clk_cpu_dvfs_node = NULL;
 struct dvfs_node *clk_gpu_dvfs_node = NULL;
 struct dvfs_node *clk_vepu_dvfs_node = NULL;
+struct dvfs_node *clk_ddr_dvfs_node = NULL;
 /*******************************************************/
 static unsigned int cpufreq_get_rate(unsigned int cpu)
 {
@@ -183,6 +184,11 @@ static int cpufreq_init_cpu0(struct cpufreq_policy *policy)
                clk_enable_dvfs(clk_vepu_dvfs_node);
        }
 
+       clk_ddr_dvfs_node = clk_get_dvfs_node("clk_ddr");
+       if (clk_ddr_dvfs_node){
+               clk_enable_dvfs(clk_ddr_dvfs_node);
+       }
+
        clk_cpu_dvfs_node = clk_get_dvfs_node("clk_core");
        if (!clk_cpu_dvfs_node){
                return -EINVAL;