R600/SI: Relax some ordering in tests.

This will help with enabling misched

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216971 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/R600/rotl.i64.ll b/test/CodeGen/R600/rotl.i64.ll
index cf4a40944a2376e4cf8b8894a7758124415fb465..a221ce3f8bfb57303e41c94c76b52bd89317e470 100644 (file)
--- a/test/CodeGen/R600/rotl.i64.ll
+++ b/test/CodeGen/R600/rotl.i64.ll
@@ -1,10 +1,11 @@
 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: @s_rotl_i64:
-; SI: S_SUB_I32
-; SI: S_LSHR_B64
-; SI: S_LSHL_B64
+; SI-DAG: S_LSHL_B64
+; SI-DAG: S_SUB_I32
+; SI-DAG: S_LSHR_B64
 ; SI: S_OR_B64
+; SI: S_ENDPGM
 define void @s_rotl_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) {
 entry:
   %0 = shl i64 %x, %y
@@ -16,11 +17,12 @@ entry:
 }
 
 ; FUNC-LABEL: @v_rotl_i64:
-; SI: V_LSHL_B64
-; SI: V_SUB_I32
+; SI-DAG: V_LSHL_B64
+; SI-DAG: V_SUB_I32
 ; SI: V_LSHR_B64
 ; SI: V_OR_B32
 ; SI: V_OR_B32
+; SI: S_ENDPGM
 define void @v_rotl_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {
 entry:
   %x = load i64 addrspace(1)* %xptr, align 8

diff --git a/test/CodeGen/R600/rotl.ll b/test/CodeGen/R600/rotl.ll
index 83f657fd4cce858d2fe1f499b810143abc5ab6cc..8c86fb5aeabcd6236147c927e60c545da7dd4d4c 100644 (file)
--- a/test/CodeGen/R600/rotl.ll
+++ b/test/CodeGen/R600/rotl.ll
@@ -20,10 +20,11 @@ entry:
 }
 
 ; FUNC-LABEL: @rotl_v2i32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: V_ALIGNBIT_B32
+; SI: S_ENDPGM
 define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
 entry:
   %0 = shl <2 x i32> %x, %y
@@ -35,14 +36,15 @@ entry:
 }
 
 ; FUNC-LABEL: @rotl_v4i32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
-; SI: S_SUB_I32
-; SI: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI-DAG: S_SUB_I32
+; SI-DAG: V_ALIGNBIT_B32
+; SI: S_ENDPGM
 define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
 entry:
   %0 = shl <4 x i32> %x, %y

diff --git a/test/CodeGen/R600/rotr.i64.ll b/test/CodeGen/R600/rotr.i64.ll
index c264751baeb1a45239135493980da08dcc4bb7e0..08dcd5204842a020becd87e01cbf256be4100f05 100644 (file)
--- a/test/CodeGen/R600/rotr.i64.ll
+++ b/test/CodeGen/R600/rotr.i64.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: @s_rotr_i64
-; SI: S_LSHR_B64
-; SI: S_SUB_I32
+; SI-DAG: S_SUB_I32
+; SI-DAG: S_LSHR_B64
 ; SI: S_LSHL_B64
 ; SI: S_OR_B64
 define void @s_rotr_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) {
@@ -16,9 +16,9 @@ entry:
 }
 
 ; FUNC-LABEL: @v_rotr_i64
-; SI: V_LSHR_B64
-; SI: V_SUB_I32
-; SI: V_LSHL_B64
+; SI-DAG: V_SUB_I32
+; SI-DAG: V_LSHR_B64
+; SI-DAG: V_LSHL_B64
 ; SI: V_OR_B32
 ; SI: V_OR_B32
 define void @v_rotr_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %xptr, i64 addrspace(1)* %yptr) {

diff --git a/test/CodeGen/R600/sext-in-reg.ll b/test/CodeGen/R600/sext-in-reg.ll
index 14f1cdf3b9532be58b17c1e814391897ab6f3f38..ba0dbcb284050af8258ce16b83e876309d11fc71 100644 (file)
--- a/test/CodeGen/R600/sext-in-reg.ll
+++ b/test/CodeGen/R600/sext-in-reg.ll
@@ -195,10 +195,11 @@ define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a,
 }
 
 ; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
-; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
-; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
-; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
-; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
+; SI-DAG: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
+; SI-DAG: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
+; SI-DAG: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
+; SI-DAG: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
+; SI: S_ENDPGM
 
 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
 ; EG-NOT: BFE