A pass to remove the worst of the replay trap offenders, and as a bonus, align basic...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30467 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h
index 6dc412b815e0fc2095a4968a143a99477abbbe38..af4db0fc13eb8d4c313903bb54865cd754d518bb 100644 (file)
--- a/lib/Target/Alpha/Alpha.h
+++ b/lib/Target/Alpha/Alpha.h
@@ -31,6 +31,8 @@ namespace llvm {
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
   FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
                                            MachineCodeEmitter &MCE);
+  FunctionPass *createAlphaLLRPPass(AlphaTargetMachine &tm);
+
 } // end namespace llvm;
 
 // Defines symbolic names for Alpha registers.  This defines a mapping from

diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
new file mode 100644 (file)
index 0000000..0ad86f4
--- /dev/null
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -0,0 +1,143 @@
+//===-- AlphaLLRP.cpp - Alpha Load Load Replay Trap elimination pass. -- --===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Andrew Lenharth and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Here we check for potential replay traps introduced by the spiller
+// We also align some branch targets if we can do so for free
+//===----------------------------------------------------------------------===//
+
+
+#include "Alpha.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/ADT/SetOperations.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/Support/CommandLine.h"
+using namespace llvm;
+
+namespace {
+  Statistic<> nopintro("alpha-nops", "Number of nops inserted");
+  Statistic<> nopalign("alpha-nops-align", 
+                      "Number of nops inserted for alignment");
+
+  cl::opt<bool>
+  AlignAll("alpha-align-all", cl::Hidden,
+                   cl::desc("Align all blocks"));
+
+  struct AlphaLLRPPass : public MachineFunctionPass {
+    /// Target machine description which we query for reg. names, data
+    /// layout, etc.
+    ///
+    AlphaTargetMachine &TM;
+
+    AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
+
+    virtual const char *getPassName() const {
+      return "Alpha NOP inserter";
+    }
+
+    bool runOnMachineFunction(MachineFunction &F) {
+      bool Changed = false;
+      MachineInstr* prev[3] = {0,0,0};
+      unsigned count = 0;
+      for (MachineFunction::iterator FI = F.begin(), FE = F.end();
+           FI != FE; ++FI) {
+       MachineBasicBlock& MBB = *FI;
+       bool ub = false;
+         for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
+           if (count%4 == 0)
+             prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
+           ++count;
+           MachineInstr *MI = I++;
+           switch (MI->getOpcode()) {
+           case Alpha::LDQ:  case Alpha::LDL:
+           case Alpha::LDWU: case Alpha::LDBU:
+           case Alpha::LDT: case Alpha::LDS:
+             
+           case Alpha::STQ:  case Alpha::STL:
+           case Alpha::STW:  case Alpha::STB:
+           case Alpha::STT: case Alpha::STS:
+             if (MI->getOperand(2).getReg() == Alpha::R30) {
+               if (prev[0] 
+                   && prev[0]->getOperand(2).getReg() == 
+                   MI->getOperand(2).getReg()
+                   && prev[0]->getOperand(1).getImmedValue() == 
+                   MI->getOperand(1).getImmedValue()) {
+                 prev[0] = prev[1];
+                 prev[1] = prev[2];
+                 prev[2] = 0;
+                 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                   .addReg(Alpha::R31); 
+                 Changed = true; nopintro += 1;
+                 count += 1;
+               } else if (prev[1] 
+                          && prev[1]->getOperand(2).getReg() == 
+                          MI->getOperand(2).getReg()
+                          && prev[1]->getOperand(1).getImmedValue() == 
+                          MI->getOperand(1).getImmedValue()) {
+                 prev[0] = prev[2];
+                 prev[1] = prev[2] = 0;
+                 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                   .addReg(Alpha::R31); 
+                 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                   .addReg(Alpha::R31);
+                 Changed = true; nopintro += 2;
+                 count += 2;
+               } else if (prev[2] 
+                          && prev[2]->getOperand(2).getReg() == 
+                          MI->getOperand(2).getReg()
+                          && prev[2]->getOperand(1).getImmedValue() == 
+                          MI->getOperand(1).getImmedValue()) {
+                 prev[0] = prev[1] = prev[2] = 0;
+                 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                   .addReg(Alpha::R31);
+                 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                   .addReg(Alpha::R31);
+                 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+                   .addReg(Alpha::R31);
+                 Changed = true; nopintro += 3;
+                 count += 3;
+               }
+               prev[0] = prev[1];
+               prev[1] = prev[2];
+               prev[2] = MI;
+               break;
+             }
+             //fall through
+           case Alpha::BR:
+           case Alpha::JMP:
+             ub = true;
+             //fall through
+           default:
+             prev[0] = prev[1];
+             prev[1] = prev[2];
+             prev[2] = 0;
+             break;
+           }
+         }
+         if (ub || AlignAll) {
+           //we can align stuff for free at this point
+           while (count % 4) {
+             BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
+               .addReg(Alpha::R31).addReg(Alpha::R31);
+             ++count;
+             ++nopalign;
+             prev[0] = prev[1];
+             prev[1] = prev[2];
+             prev[2] = 0;
+           }
+         }
+      }
+      return Changed;
+    }
+  };
+} // end of anonymous namespace
+
+FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
+  return new AlphaLLRPPass(tm);
+}

diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp
index b752e4c1043f50cb2641ffc44a8156c88b0da663..6204998b24063869b2f16f549b536f28c609c957 100644 (file)
--- a/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -77,6 +77,7 @@ bool AlphaTargetMachine::addPreEmitPass(FunctionPassManager &PM, bool Fast) {
 }
 bool AlphaTargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast, 
                                             std::ostream &Out) {
+  PM.add(createAlphaLLRPPass(*this));
   PM.add(createAlphaCodePrinterPass(Out, *this));
   return false;
 }