Fix a major miscompilation where we were overwriting the scale reg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19511 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index a796045c5b50466a289b7f76b4eb2cdadaaf6f37..b3a93b11e400eee7bb0e0ccf50961040813c470e 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -469,7 +469,7 @@ bool ISel::SelectAddress(SDOperand N, X86AddressMode &AM) {
     AM.Disp += cast<ConstantSDNode>(N)->getValue();
     return false;
   case ISD::SHL:
-    if (AM.IndexReg == 0 || AM.Scale == 1)
+    if (AM.IndexReg == 0 && AM.Scale == 1)
       if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
         unsigned Val = CN->getValue();
         if (Val == 1 || Val == 2 || Val == 3) {