(IntVT (X86VAlign RC:$src2, RC:$src1,
(i8 imm:$src3))))]>, EVEX_4V;
- let Constraints = "$src0 = $dst", AddedComplexity=30 in
+ let Constraints = "$src0 = $dst" in
def rrik : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
(ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2, i8imm:$src3),
!strconcat("valign"##Suffix,
- " \t{$src3, $src2, $src1, $mask, $dst|"
- "$dst, $mask, $src1, $src2, $src3}"),
+ " \t{$src3, $src2, $src1, $dst {${mask}}|"
+ "$dst {${mask}}, $src1, $src2, $src3}"),
[(set RC:$dst,
(IntVT (vselect KRC:$mask,
(X86VAlign RC:$src2, RC:$src1,
define <8 x i64> @test_mask_valign_q(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) {
; CHECK-LABEL: test_mask_valign_q:
-; CHECK: valignq $2, %zmm1, %zmm0, %k1, %zmm2
+; CHECK: valignq $2, %zmm1, %zmm0, %zmm2 {%k1}
%res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i8 2, <8 x i64> %src, i8 %mask)
ret <8 x i64> %res
}
// CHECK: encoding: [0x62,0x32,0x4d,0xc2,0x7e,0x24,0xad,0x05,0x00,0x00,0x00]
vpermt2d 5(,%r13,4), %zmm22, %zmm12 {%k2} {z}
-// CHECK: valignq
+// CHECK: valignq $2
// CHECK: encoding: [0x62,0xf3,0xfd,0x48,0x03,0x4c,0x24,0x04,0x02]
valignq $2, 0x100(%rsp), %zmm0, %zmm1
+
+// CHECK: valignq $3
+// CHECK: encoding: [0x62,0xf3,0xfd,0x49,0x03,0xcb,0x03]
+valignq $3, %zmm3, %zmm0, %zmm1 {%k1}