Add a perf optzn corresponding to PR1033.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32229 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/README-SSE.txt b/lib/Target/X86/README-SSE.txt
index 2685956dc1aabd06a6112e0194aedfaf66d8686e..b80661a5b79594cdfd2d6ec643decd5080f43e04 100644 (file)
--- a/lib/Target/X86/README-SSE.txt
+++ b/lib/Target/X86/README-SSE.txt
@@ -18,6 +18,11 @@ Think about doing i64 math in SSE regs.
 
 //===---------------------------------------------------------------------===//
 
+Bitcast to<->from SSE registers should use movd/movq instead of going through
+the stack.  Testcase here: CodeGen/X86/bitcast.ll
+
+//===---------------------------------------------------------------------===//
+
 This testcase should have no SSE instructions in it, and only one load from
 a constant pool: