Mark these instructions clobbersPred. They modify the condition code register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 9421885bc5353e932f9b1e2dad9b068366dc079c..76358242314981cf4329ad31dd41b5668b37082d 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -612,7 +612,7 @@ let isLoad = 1, isReturn = 1, isTerminator = 1 in
                     "ldm${p}${addr:submode} $addr, $dst1",
                     []>;
 
-let isCall = 1, noResults = 1, 
+let isCall = 1, noResults = 1, clobbersPred = 1,
   Defs = [R0, R1, R2, R3, R12, LR,
           D0, D1, D2, D3, D4, D5, D6, D7] in {
   def BL  : AXI<(ops i32imm:$func, variable_ops),
@@ -806,12 +806,14 @@ def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
 // These aren't really mov instructions, but we have to define them this way
 // due to flag operands.
 
+let clobbersPred = 1 in {
 def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
                       "mov", "s $dst, $src, lsr #1",
                       [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
 def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
                       "mov", "s $dst, $src, asr #1",
                       [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
+}
 def MOVrx       : AI1<(ops GPR:$dst, GPR:$src),
                       "mov", " $dst, $src, rrx",
                       [(set GPR:$dst, (ARMrrx GPR:$src))]>;
@@ -860,17 +862,22 @@ defm UXTAH : AI_bin_rrot<"uxtah",
 //
 
 defm ADD  : AI1_bin_irs<"add", "" , BinOpFrag<(add  node:$LHS, node:$RHS)>>;
-defm ADDS : AI1_bin_irs<"add", "s", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
 defm ADC  : AI1_bin_irs<"adc", "" , BinOpFrag<(adde node:$LHS, node:$RHS)>>;
 defm SUB  : AI1_bin_irs<"sub", "" , BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
-defm SUBS : AI1_bin_irs<"sub", "s", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
 defm SBC  : AI1_bin_irs<"sbc", "" , BinOpFrag<(sube node:$LHS, node:$RHS)>>;
 
+let clobbersPred = 1 in {
+defm ADDS : AI1_bin_irs<"add", "s", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
+defm SUBS : AI1_bin_irs<"sub", "s", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
+}
+
 // These don't define reg/reg forms, because they are handled above.
 defm RSB  : AI1_bin_is <"rsb", "" , BinOpFrag<(sub  node:$RHS, node:$LHS)>>;
-defm RSBS : AI1_bin_is <"rsb", "s", BinOpFrag<(subc node:$RHS, node:$LHS)>>;
 defm RSC  : AI1_bin_is <"rsc", "" , BinOpFrag<(sube node:$RHS, node:$LHS)>>;
 
+let clobbersPred = 1 in
+defm RSBS : AI1_bin_is <"rsb", "s", BinOpFrag<(subc node:$RHS, node:$LHS)>>;
+
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
 def : ARMPat<(add    GPR:$src, so_imm_neg:$imm),
              (SUBri  GPR:$src, so_imm_neg:$imm)>;
@@ -1094,18 +1101,20 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
 //  Comparison Instructions...
 //
 
+let clobbersPred = 1 in {
 defm CMP  : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
 defm CMN  : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
 
-def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
-             (CMNri  GPR:$src, so_imm_neg:$imm)>;
-
 // Note that TST/TEQ don't set all the same flags that CMP does!
 defm TST  : AI1_bin0_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
 defm TEQ  : AI1_bin0_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
 
 defm CMPnz : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
 defm CMNnz : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
+}
+
+def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
+             (CMNri  GPR:$src, so_imm_neg:$imm)>;
 
 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
              (CMNri  GPR:$src, so_imm_neg:$imm)>;
@@ -1148,7 +1157,7 @@ def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
 //
 
 // __aeabi_read_tp preserves the registers r1-r3.
-let isCall = 1,
+let isCall = 1, clobbersPred = 1,
   Defs = [R0, R12, LR] in {
   def TPsoft : AXI<(ops),
                "bl __aeabi_read_tp",

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index d2c1db6c959e4b1458033166407292b547b0d510..9ea39a6e013a2daf02a38a70bb9a008e956d4fae 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -33,6 +33,7 @@ class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
              string asm, string cstr, list<dag> pattern>
   // FIXME: Set all opcodes to 0 for now.
   : InstARM<0, am, sz, IndexModeNone, cstr> {
+  let clobbersPred = 1;
   let OperandList = ops;
   let AsmString   = asm;
   let Pattern = pattern;

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index c0428e96b3952e698e9851454a6b50d2c4fc6685..73a3b37bcd8be822116ad5b66cb94fc10c29b574 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -277,7 +277,7 @@ def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2),
 
 // FMSRR: GPR -> SPR
 
-
+let clobbersPred = 1 in
 def FMSTAT : ASI<(ops), "fmstat", "", [(arm_fmstat)]>;
 
 // FMXR: GPR -> VFP Sstem reg