const ARMSubtarget *STI;
ARMFunctionInfo *AFI;
RegScavenger *RS;
- bool isThumb2;
+ bool isThumb1, isThumb2;
bool runOnMachineFunction(MachineFunction &Fn) override;
STI = &TM.getSubtarget<ARMSubtarget>();
RS = new RegScavenger();
isThumb2 = AFI->isThumb2Function();
+ isThumb1 = AFI->isThumbFunction() && !isThumb2;
+
+ // Don't do anything in this pass with Thumb1 for now.
+ if (isThumb1) return false;
bool Modified = false;
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
MRI = &Fn.getRegInfo();
MF = &Fn;
+ ARMFunctionInfo *AFI = Fn.getInfo<ARMFunctionInfo>();
+ bool isThumb1 = AFI->isThumbFunction() && !AFI->isThumb2Function();
+ // Don't do anything in this pass with Thumb1 for now.
+ if (isThumb1) return false;
+
bool Modified = false;
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
++MFI)
}
bool ARMPassConfig::addPreRegAlloc() {
- // FIXME: temporarily disabling load / store optimization pass for Thumb1.
- if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
+ if (getOptLevel() != CodeGenOpt::None)
addPass(createARMLoadStoreOptimizationPass(true));
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
addPass(createMLxExpansionPass());
}
bool ARMPassConfig::addPreSched2() {
- // FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None) {
- if (!getARMSubtarget().isThumb1Only()) {
- addPass(createARMLoadStoreOptimizationPass());
- printAndVerify("After ARM load / store optimizer");
- }
+ addPass(createARMLoadStoreOptimizationPass());
+ printAndVerify("After ARM load / store optimizer");
+
if (getARMSubtarget().hasNEON())
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
}