Fix another batch of VLD/VST decoding crashes discovered by randomized testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 725a8a2abd4aaec3e902c063bd6d712ff88a4310..ad1692ca3b8253692366693092bc6f4fe4ad0989 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2769,8 +2769,11 @@ static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2819,8 +2822,11 @@ static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2876,8 +2882,11 @@ static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2931,8 +2940,11 @@ static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2989,8 +3001,11 @@ static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) { 
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -3043,8 +3058,11 @@ static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -3103,8 +3121,11 @@ static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -3158,8 +3179,11 @@ static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));

diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
index b909c4bb4bc3483485d2cbbaf9cb5946c4098837..6068a38c3d3e0dec1b1b1dc55eebb3a8698a987b 100644 (file)
--- a/test/MC/Disassembler/ARM/neon.txt
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -1848,4 +1848,6 @@
 
 0x0 0xc 0xa0 0xf4
 # CHECK: vld1.8        {d0[]}, [r0], r0
+0x0d 0x03 0x80 0xf4
+# CHECK: vst4.8        {d0[0], d1[0], d2[0], d3[0]}, [r0]!