/// none is found.
int findFirstPredOperandIdx() const;
- /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
+ /// isRegReDefinedByTwoAddr - Given the index of a register def operand,
/// check if the register def is a re-definition due to two addr elimination.
- bool isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const;
+ bool isRegReDefinedByTwoAddr(unsigned DefIdx) const;
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
///
// must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is one of the
// def-and-use register operand.
- if (mi->isRegReDefinedByTwoAddr(interval.reg, MOIdx)) {
+ if (mi->isRegReDefinedByTwoAddr(MOIdx)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we
return -1;
}
-/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
+/// isRegReDefinedByTwoAddr - Given the index of a register def operand,
/// check if the register def is a re-definition due to two addr elimination.
-bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
+bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{
+ assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!");
const TargetInstrDesc &TID = getDesc();
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
- if (MO.isReg() && MO.isUse() && MO.getReg() == Reg &&
+ if (MO.isReg() && MO.isUse() &&
TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
return true;
}
if (Reg == 0) continue;
if (!MO.isDef()) continue;
// Ignore two-addr defs.
- if (MI->isRegReDefinedByTwoAddr(Reg, i)) continue;
+ if (MI->isRegReDefinedByTwoAddr(i)) continue;
DefIndices[Reg] = Count;
KillIndices[Reg] = -1;
// Check if this is a two address instruction. If so, then
// the def does not kill the use.
if (last->second.first == I &&
- I->isRegReDefinedByTwoAddr(MO.getReg(), i))
+ I->isRegReDefinedByTwoAddr(i))
continue;
MachineOperand& lastUD =