clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX

Change-Id: I46e8c54de7c74c1abb001512198176ee51b638ac
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index dc7fe86b9fb4f42203cc1b5cd1c34bfde2813cd4..b5a95d87888a197c2927ee15a72e005db4a88c7a 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -591,7 +591,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
                        RK3399_CLKGATE_CON(8), 15, GFLAGS),
 
        COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
-                       RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
+                       RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
                        RK3399_CLKGATE_CON(10), 6, GFLAGS),
        /* i2s */
        COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,