dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe controller

Add a binding that describes the Rockchip PCIe controller found on Rockchip
SoCs PCIe interface.

Change-Id: Ifb84320315c06759612f2b3d9b2b6ff3e1e5cb1e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
index 69a080485c7ef30a9116fbab09c5d1acb301abad..ba67b39939c10b15f7e1a99291c935a1c2c81bf8 100644 (file)
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -7,87 +7,100 @@ Required properties:
                interrupt source. The value must be 1.
 - compatible: Should contain "rockchip,rk3399-pcie"
 - reg: Two register ranges as listed in the reg-names property
-- reg-names: The first entry must be "axi-base" for the core registers
-       The second entry must be "apb-base" for the client pcie registers
+- reg-names: Must include the following names
+       - "axi-base"
+       - "apb-base"
 - clocks: Must contain an entry for each entry in clock-names.
                See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
-       - "aclk_pcie"
-       - "aclk_perf_pcie"
-       - "hclk_pcie"
-       - "clk_pciephy_ref"
+       - "aclk"
+       - "aclk-perf"
+       - "hclk"
+       - "pm"
+- msi-map: Maps a Requester ID to an MSI controller and associated
+       msi-specifier data. See ./pci-msi.txt
+- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+- phy-names:  MUST be "pcie-phy".
 - interrupts: Three interrupt entries must be specified.
 - interrupt-names: Must include the following names
-       - "pcie-sys"
-       - "pcie-legacy"
-       - "pcie-client"
+       - "sys"
+       - "legacy"
+       - "client"
 - resets: Must contain five entries for each entry in reset-names.
           See ../reset/reset.txt for details.
 - reset-names: Must include the following names
-       - "phy-rst"
-       - "core-rst"
-       - "mgmt-rst"
-       - "mgmt-sticky-rst"
-       - "pipe-rst"
-- rockchip,grf: phandle to the syscon managing the "general register files"
-- pcie-conf: offset of pcie client block for  configuration
-- pcie-status: offset of pcie client block for status
-- pcie-laneoff: offset of pcie client block for lane
-- msi-parent: Link to the hardware entity that serves as the Message
+       - "core"
+       - "mgmt"
+       - "mgmt-sticky"
+       - "pipe"
 - pinctrl-names : The pin control state names
 - pinctrl-0: The "default" pinctrl state
+- #interrupt-cells: specifies the number of cells needed to encode an
+       interrupt source. The value must be 1.
 - interrupt-map-mask and interrupt-map: standard PCI properties
-- interrupt-controller: identifies the node as an interrupt controller
 
 Optional Property:
 - ep-gpios: contain the entry for pre-reset gpio
 - num-lanes: number of lanes to use
-- assigned-clocks, assigned-clock-parents and assigned-clock-rates: standard
-                  clock bindings. See ../clock/clock-bindings.txt
+- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
+- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
+- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
+
+*Interrupt controller child node*
+The core controller provides a single interrupt for legacy INTx. The PCIe node
+should contain an interrupt controller node as a target for the PCI
+'interrupt-map' property. This node represents the domain at which the four
+INTx interrupts are decoded and routed.
+
+
+Required properties for Interrupt controller child node:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+       address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+       interrupt source. The value must be 1.
 
 Example:
 
-pci_express: axi-pcie@f8000000 {
+pcie0: pcie@f8000000 {
+       compatible = "rockchip,rk3399-pcie";
        #address-cells = <3>;
        #size-cells = <2>;
-       compatible = "rockchip,rk3399-pcie";
        clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
-                <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
-       clock-names = "aclk_pcie", "aclk_perf_pcie",
-                     "hclk_pcie", "clk_pciephy_ref";
+                <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+       clock-names = "aclk", "aclk-perf",
+                     "hclk", "pm";
        bus-range = <0x0 0x1>;
-       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
-                    <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-       interrupt-names: "pcie-sys", "pcie-legacy", "pcie-client";
+       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
+                    <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
+                    <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
+       interrupt-names = "sys", "legacy", "client";
        assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
        assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
        assigned-clock-rates = <100000000>;
        ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
-       ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
-                  0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
+       ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
+                 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
        num-lanes = <4>;
-       reg = < 0x0 0xf8000000 0x0 0x2000000 >, < 0x0 0xfd000000 0x0 0x1000000 >;
-       reg-name = "axi-base", "apb-base";
-       resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+       msi-map = <0x0 &its 0x0 0x1000>;
+       reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
+       reg-names = "axi-base", "apb-base";
+       resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
                 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
-       reset-names = "phy-rst", "core-rst", "mgmt-rst", "mgmt-sticky-rst", "pipe-rst";
-       rockchip,grf = <&grf>;
-       pcie-conf = <0xe220>;
-       pcie-status = <0xe2a4>;
-       pcie-laneoff = <0xe214>;
+       reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
+       phys = <&pcie_phy>;
+       phy-names = "pcie-phy";
        pinctrl-names = "default";
        pinctrl-0 = <&pcie_clkreq>;
-       msi-parent = <&its>;
        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 7>;
-       interrupt-map = <0 0 0 1 &pcie_0 1>,
-                       <0 0 0 2 &pcie_0 2>,
-                       <0 0 0 3 &pcie_0 3>,
-                       <0 0 0 4 &pcie_0 4>;
-       pcie_0: interrupt-controller {
+       interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+                       <0 0 0 2 &pcie0_intc 1>,
+                       <0 0 0 3 &pcie0_intc 2>,
+                       <0 0 0 4 &pcie0_intc 3>;
+       pcie0_intc: interrupt-controller {
                interrupt-controller;
                #address-cells = <0>;
                #interrupt-cells = <1>;
        };
-
 };